A 0.20–2.43 GHz fractional-N frequency synthesizer is presented for multi-band wireless communication systems,in which the scheme adopts low phase noise voltage-controlled oscillators(VCOs)and a charge pump(CP)with r...A 0.20–2.43 GHz fractional-N frequency synthesizer is presented for multi-band wireless communication systems,in which the scheme adopts low phase noise voltage-controlled oscillators(VCOs)and a charge pump(CP)with reduced current mismatch.VCOs that determine the out-band phase noise of a phase-locked loop(PLL)based frequency synthesizer are optimized using an automatic amplitude control technique and a high-quality factor figure-8-shaped inductor.A CP with a mismatch suppression architecture is proposed to improve the current match of the CP and reduce the PLL phase errors.Theoretical analysis is presented to investigate the influence of the current mismatch on the output performance of PLLs.Fabricated in a TSMC 0.18-μm CMOS process,the prototype operates from 0.20 to 2.43 GHz.The PLL synthesizer achieves an in-band phase noise of-96.8 dBc/Hz and an out-band phase noise of-122.8 dBc/Hz at the 2.43-GHz carrier.The root-mean-square jitter is 1.2 ps under the worst case,and the measured reference spurs are less than-65.3 dBc.The current consumption is 15.2 mA and the die occupies 850μm×920μm.展开更多
This paper presents a 10-GHz low spur and low jitter phase-locked loop（PLL）.An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of th...This paper presents a 10-GHz low spur and low jitter phase-locked loop（PLL）.An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler’s noise and the charge pump’s current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter is 757 fs（1 kHz to 10 MHz）;the phase noise is-89 and-118.1 dBc/Hzat 10kHz and 1 MHz frequency offset,respectively;and the reference frequency spur is below -77 dBc.The chip size is 0.32 mm2 and the power consumption is 30.6 mW.展开更多
A new high performance charge pump circuit is designed and realized in 0.18μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge...A new high performance charge pump circuit is designed and realized in 0.18μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range.Furthermore,a method of adding a precharging current source is proposed to increase the initial charge current,which will speed up the settling time of CPPLLs.Test results show that the current mismatching can be less than 0.4%in the output voltage range of 0.4 to 1.7 V,with a charge pump current of 100μA and a precharging current of 70μA.The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.展开更多
基金Project supported by the National Natural Science Foundation of China(No.61376031)。
文摘A 0.20–2.43 GHz fractional-N frequency synthesizer is presented for multi-band wireless communication systems,in which the scheme adopts low phase noise voltage-controlled oscillators(VCOs)and a charge pump(CP)with reduced current mismatch.VCOs that determine the out-band phase noise of a phase-locked loop(PLL)based frequency synthesizer are optimized using an automatic amplitude control technique and a high-quality factor figure-8-shaped inductor.A CP with a mismatch suppression architecture is proposed to improve the current match of the CP and reduce the PLL phase errors.Theoretical analysis is presented to investigate the influence of the current mismatch on the output performance of PLLs.Fabricated in a TSMC 0.18-μm CMOS process,the prototype operates from 0.20 to 2.43 GHz.The PLL synthesizer achieves an in-band phase noise of-96.8 dBc/Hz and an out-band phase noise of-122.8 dBc/Hz at the 2.43-GHz carrier.The root-mean-square jitter is 1.2 ps under the worst case,and the measured reference spurs are less than-65.3 dBc.The current consumption is 15.2 mA and the die occupies 850μm×920μm.
基金Project supported by the National High Technology Research and Development Program of China(No.2009AA011605)
文摘This paper presents a 10-GHz low spur and low jitter phase-locked loop（PLL）.An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler’s noise and the charge pump’s current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter is 757 fs（1 kHz to 10 MHz）;the phase noise is-89 and-118.1 dBc/Hzat 10kHz and 1 MHz frequency offset,respectively;and the reference frequency spur is below -77 dBc.The chip size is 0.32 mm2 and the power consumption is 30.6 mW.
基金Project supported by the National High Technology Research and Development Program of China(No.2007AA01Z2A7)
文摘A new high performance charge pump circuit is designed and realized in 0.18μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range.Furthermore,a method of adding a precharging current source is proposed to increase the initial charge current,which will speed up the settling time of CPPLLs.Test results show that the current mismatching can be less than 0.4%in the output voltage range of 0.4 to 1.7 V,with a charge pump current of 100μA and a precharging current of 70μA.The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.
