Now a days,MOS Current Mode Logic(MCML)has emerged as a better alternative to Complementary Metal Oxide Semiconductor(CMOS)logic in digital circuits.Recent works have only traditional logic gates that have issues with...Now a days,MOS Current Mode Logic(MCML)has emerged as a better alternative to Complementary Metal Oxide Semiconductor(CMOS)logic in digital circuits.Recent works have only traditional logic gates that have issues with information loss.Reversible logic is incorporated with MOS Current Mode Logic(MCML)in this proposed work to solve this problem,which is used for multiplier design,D Flip-Flop(DFF)and register.The minimization of power and area is the main aim of the work.In reversible logic,the count of outputs and inputs is retained as the same value for creating one-to-one mapping.A unique output vector set can be generated for each input vector set and information loss is also prevented.In reversible MCML based multiplier,reversible logic full adder is utilized to minimize the area and power.D flip-flops based on reversible MCML are often designed to store information that is then combined to form a reversible MCML based register.The proposed reversible MCML multiplier attains average power of 0.683 mW,Reversible MCML based DFF achieves 0.56μW and Reversible MCML based 8-bit register attains 04.04μW.The result shows that the proposed Reversible MCML based multiplier,Reversible MCML based D flip-flop and ReversibleMCML based register achieves better performance in terms of current,power dissipation,average power and area.展开更多
This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for tes...This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for testing CML gates. It is then proved that switching the order in which inputs are applied to a gate will affect the minimum test set;this is not the case in conventional voltage mode gates. Both the circuit output and its inverse have to be monitored to reduce the size of the test set.展开更多
By applying switch-signal theory, the interaction between MOS transmission switch-ing transistor and current signal in current-mode CMOS circuits is analyzed, and the theory oftransmission current-switches which is su...By applying switch-signal theory, the interaction between MOS transmission switch-ing transistor and current signal in current-mode CMOS circuits is analyzed, and the theory oftransmission current-switches which is suitable to current-mode CMOS circuits is proposed. Thecircuits, such as ternary full-adder etc., designed by using this theory have simpler circuit struc-tures and correct logic functions. It is confirmed that this theory is efficient in guiding the logicdesign of current-mode CMOS circuits at switch level.展开更多
By applying switch-signal theory, the theory of transmission current-switches based on symmetric ternary logic is proposed, this theory is suitable to design symmetric ternary current-mode CMOS circuits. The symmetric...By applying switch-signal theory, the theory of transmission current-switches based on symmetric ternary logic is proposed, this theory is suitable to design symmetric ternary current-mode CMOS circuits. The symmetric ternary current-mode CMOS circuits designed by using this theory not only have simpler circuit structures and correct logic functions, but also can process bidirectional signals.展开更多
In order to improve the performance of arithmetic very large-scale integration （VLSI） sys- tem, a novel structure of quaternary logic gates is proposed based on multiple-valued current mode （MVCM） by using dynamic...In order to improve the performance of arithmetic very large-scale integration （VLSI） sys- tem, a novel structure of quaternary logic gates is proposed based on multiple-valued current mode （MVCM） by using dynamic source-coupled logic （SCL）. Its key components, the comparator and the output generator are both based on differential-pair circuit （DPC）, and the latter is constructed by using the structure of DPC trees. The pre-charge evaluates logic style makes a steady current flow cut off, thereby greatly saving the power dissipation. The combination of multiple-valued source- coupled logic and differential-pair circuit makes it lower power consumption and more compact. The performance is evaluated by HSPICE simulation with 0.18 ~m CMOS technology. The power dissipa- tion, transistor numbers and delay are superior to corresponding binary CMOS implementation. Mul- tiple-valued logic will be the potential solution for the high performance arithmetic VLSI system in the future.展开更多
In this paper, a phase interpolator clock and data recovery （CDR） with low-voltage current mode logic （CML） latched, buffers, and muxes is presented. Because of using the CML circuits, the CDR can operate in a low...In this paper, a phase interpolator clock and data recovery （CDR） with low-voltage current mode logic （CML） latched, buffers, and muxes is presented. Because of using the CML circuits, the CDR can operate in a low supply voltage. And the original swing of the differential inputs and outputs is less than that of the CMOS logic. The power supply voltage is 1.2 V, and the static current consumption is about 20 mA. In this phase interpolator CDR, the charge pump and loop filter are replaced by a digital filter. And this structure offers the benefits of increased system stability and faster acquisition.展开更多
This paper proposes a low-power MOS current mode logic （MCML） circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage cu...This paper proposes a low-power MOS current mode logic （MCML） circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The 16× 16 bit parallel multiplier is designed with the proposed technology. Comparing with the previous MCML circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/258. This circuit is designed with Samsung 0.35 um complementary metal oxide semiconductor （CMOS） process. The validity and effectiveness are verified through the HSPICE simulation.展开更多
文摘Now a days,MOS Current Mode Logic(MCML)has emerged as a better alternative to Complementary Metal Oxide Semiconductor(CMOS)logic in digital circuits.Recent works have only traditional logic gates that have issues with information loss.Reversible logic is incorporated with MOS Current Mode Logic(MCML)in this proposed work to solve this problem,which is used for multiplier design,D Flip-Flop(DFF)and register.The minimization of power and area is the main aim of the work.In reversible logic,the count of outputs and inputs is retained as the same value for creating one-to-one mapping.A unique output vector set can be generated for each input vector set and information loss is also prevented.In reversible MCML based multiplier,reversible logic full adder is utilized to minimize the area and power.D flip-flops based on reversible MCML are often designed to store information that is then combined to form a reversible MCML based register.The proposed reversible MCML multiplier attains average power of 0.683 mW,Reversible MCML based DFF achieves 0.56μW and Reversible MCML based 8-bit register attains 04.04μW.The result shows that the proposed Reversible MCML based multiplier,Reversible MCML based D flip-flop and ReversibleMCML based register achieves better performance in terms of current,power dissipation,average power and area.
文摘This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for testing CML gates. It is then proved that switching the order in which inputs are applied to a gate will affect the minimum test set;this is not the case in conventional voltage mode gates. Both the circuit output and its inverse have to be monitored to reduce the size of the test set.
基金Supported by National Natural Science Foundation of China
文摘By applying switch-signal theory, the interaction between MOS transmission switch-ing transistor and current signal in current-mode CMOS circuits is analyzed, and the theory oftransmission current-switches which is suitable to current-mode CMOS circuits is proposed. Thecircuits, such as ternary full-adder etc., designed by using this theory have simpler circuit struc-tures and correct logic functions. It is confirmed that this theory is efficient in guiding the logicdesign of current-mode CMOS circuits at switch level.
基金National Natural Science Foundation of ChinaNatural science Foundation of Zhejiang Province
文摘By applying switch-signal theory, the theory of transmission current-switches based on symmetric ternary logic is proposed, this theory is suitable to design symmetric ternary current-mode CMOS circuits. The symmetric ternary current-mode CMOS circuits designed by using this theory not only have simpler circuit structures and correct logic functions, but also can process bidirectional signals.
基金Supported by Beijing Institute of Technology Science Foundation(3050012211106)
文摘In order to improve the performance of arithmetic very large-scale integration （VLSI） sys- tem, a novel structure of quaternary logic gates is proposed based on multiple-valued current mode （MVCM） by using dynamic source-coupled logic （SCL）. Its key components, the comparator and the output generator are both based on differential-pair circuit （DPC）, and the latter is constructed by using the structure of DPC trees. The pre-charge evaluates logic style makes a steady current flow cut off, thereby greatly saving the power dissipation. The combination of multiple-valued source- coupled logic and differential-pair circuit makes it lower power consumption and more compact. The performance is evaluated by HSPICE simulation with 0.18 ~m CMOS technology. The power dissipa- tion, transistor numbers and delay are superior to corresponding binary CMOS implementation. Mul- tiple-valued logic will be the potential solution for the high performance arithmetic VLSI system in the future.
基金supported by the Fundamental Research Funds for the Central Universities under Grant No.2009JBM001
文摘In this paper, a phase interpolator clock and data recovery （CDR） with low-voltage current mode logic （CML） latched, buffers, and muxes is presented. Because of using the CML circuits, the CDR can operate in a low supply voltage. And the original swing of the differential inputs and outputs is less than that of the CMOS logic. The power supply voltage is 1.2 V, and the static current consumption is about 20 mA. In this phase interpolator CDR, the charge pump and loop filter are replaced by a digital filter. And this structure offers the benefits of increased system stability and faster acquisition.
文摘This paper proposes a low-power MOS current mode logic （MCML） circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The 16× 16 bit parallel multiplier is designed with the proposed technology. Comparing with the previous MCML circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/258. This circuit is designed with Samsung 0.35 um complementary metal oxide semiconductor （CMOS） process. The validity and effectiveness are verified through the HSPICE simulation.
文摘光纤通信在大数据时代得到广泛的应用,其速度快、带宽大、可靠性高的特点满足了对长距离、大容量信息传输的要求。前置放大器作为光接收器的前端,其性能高低直接影响到整个光接收系统的工作性能。基于SMIC 0.13μm CMOS工艺,设计完成了一款5 Gbps光接收前置放大器。首先,整体差分式结构可以消除共模噪声的干扰,降低放大器的等效输入噪声。其次,采用共源共栅的输入结构具有低输入阻抗的特点,能有效抑制光电管大电容带来的不利影响。最后,输出级采用电流模逻辑结构,解决了输出增益与带宽之间的矛盾。仿真结果表明,放大器增益达到62 d BΩ,带宽4.7 GHz;等效输入噪声30.1 p A/Hz,眼图迹线清晰,张开度较大,能够满足5 Gbps平衡光探测器通信要求。
