A High Gain, Noise Cancelling 2515-4900 MHz CMOS LNA for China Mobile 5G Communication Application

With the development of the times,people’s requirements for communication technology are becoming higher and higher.4G communication technology has been unable to meet development needs,and 5G communication technology has emerged as the times require.This article proposes the design of a low-noise amplifier(LNA)that will be used in the 5G band of China Mobile Communications.A low noise amplifier for mobile 5G communication is designed based on Taiwan Semiconductor Manufacturing Company(TSMC)0.13μm Radio Frequency(RF)Complementary Metal Oxide Semiconductor(CMOS)process.The LNA employs self-cascode devices in current-reuse configuration to enable lower supply voltage operation without compromising the gain.This design uses an active feedback amplifier to achieve input impedance matching,avoiding the introduction of resistive negative feedback to reduce gain.A common source(CS)amplifier is used as the input of the low noise amplifier.In order to achieve the low power consumption of LNA,current reuse technology is used to reduce power consumption.Noise cancellation techniques are used to eliminate noise.The simulation results in a maximum power gain of 22.783,the reverse isolation(S12)less than-48.092 dB,noise figure(NF)less than 1.878 dB,minimum noise figure(NFmin)=1.203 dB,input return loss(S11)and output return loss(S22)are both less than-14.933 dB in the frequency range of 2515-4900 MHz.The proposed Ultra-wideband(UWB)LNA consumed 1.424 mW without buffer from a 1.2 V power supply.

A 0.18μm CMOS low noise amplifier using a current reuse technique for 3.1-10.6 GHz UWB receivers

A new,low complexity,ultra-wideband 3.1-10.6 GHz low noise amplifier（LNA）,designed in a chartered 0.18μm RFCMOS technology,is presented.The ultra-wideband LNA consists of only two simple amplifiers with an inter-stage inductor connected.The first stage utilizing a resistive current reuse and dual inductive degeneration technique is used to attain a wideband input matching and low noise figure.A common source amplifier with an inductive peaking technique as the second stage achieves high flat gain and wide -3 dB bandwidth of the overall amplifier simultaneously.The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB,and a high reverse isolation of—45 dB,and good input/output return losses are better than -10 dB in the frequency range of 3.1-10.6 GHz.An excellent noise figure（NF） of 2.8-4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V.An input-referred third-order intercept point（IIP3） is -7.1 dBm at 6 GHz.The chip area,including testing pads,is only 0.8×0.9 mm2.

Low power fast settling multi-standard current reusing CMOS fractional-N frequency synthesizer

A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer. An auxiliary non-volatile memory （NVM） is embedded to avoid the repetitive calibration process and to save power in practical application. This PLL is implemented in a 0.18 #m technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5 #s over the entire frequency range. The LC-VCO with the stacked divide-by-2 has a good figure of merit of-193.5 dBc/Hz. The measured phase noise of frequency synthesizer is about -115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than -52 dBc. The whole frequency synthesizer consumes only 4.35 mA @ 1.8 V.

0.9 GHz and 2.4 GHz dual-band SiGe HBT LNA

This paper presents design and implementation of a dual-band LNA using a 0.35 #m SiGe HBT process for 0.9 GHz GSM and 2.4 GHz WLAN applications. PCB layout parasitic effects have a vital effect on circuit performance and are accounted for using electro-magnetic （EM） simulation. Design considerations of noise decoupling, input/output impedance matching, and current reuse are described in detail. At 0.9/2.4 GHz, gain and noise figure are 13/16 dB and 4.2/3.9 dB, respectively. Both S11 and S22 are below -10 dB. Power dissipation is 40 mW at 3.5 V supply.

Folded down-conversion mixer for a 60 GHz receiver architecture in 65-nm CMOS technology

We present the design of a folded down-conversion mixer which is incorporated at the final down-conversion stage of a 60 GHz receiver. The mixer employs an ac-coupled current reuse transconductance stage. It performs well under low supply voltages, and is less sensitive to temperature variations and process spread. The mixer operates at an input radio frequency(RF) band ranging from 10.25 to 13.75 GHz, with a fixed local oscillator(LO) frequency of 12 GHz, which down-converts the RF band to an intermediate frequency(IF) band ranging from dc to 1.75 GHz. The mixer is designed in a 65 nm low power(LP) CMOS process with an active chip area of only 0.0179 mm2. At a nominal supply voltage of 1.2 V and an IF of 10 MHz, a maximum voltage conversion gain(VCG) of 9.8 d B, a double sideband noise figure(DSB-NF) of 11.6 d B, and a linearity in terms of input 1 d B compression point(Pin,1d B) of-13 d Bm are measured. The mixer draws a current of 5 m A from a 1.2 V supply dissipating a power of only 6 m W.

A 0.18μm CMOS single-inductor single-stage quadrature frontend for GNSS receiver

This paper presents an improved merged architecture for a low-IF GNSS receiver frontend,where the bias current and functions are reused in a stacked quadrature LNA-mixer-VCO.Only a single spiral inductor is implemented for the LC resonator and an extra 1/2 frequency divider is added as the quadrature LO signal generator. The details of the design are presented.The gain plan and noise figure are discussed.The phase noise,quadrature accuracy and power consumption are improved.The test chip is fabricated though a 0.18μm RF CMOS process. The measured noise figure is 5.4 dB on average,with a gain of 43 dB and a IIP3 of-39 dBm.The measured phase noise is better than -105 dBc/Hz at 1 MHz offset.The total power consumption is 19.8 mW with a 1.8 V supply. The experimental results satisfy the requirements for GNSS applications.