Channel estimation in integrated radar and communication systems with power amplifier distortion

To reduce the negative impact of the power amplifier(PA)nonlinear distortion caused by the orthogonal frequency division multiplexing(OFDM)waveform with high peak-to-average power ratio(PAPR)in integrated radar and communication(RadCom)systems is studied,the channel estimation in passive sensing scenarios.Adaptive channel estimation methods are proposed based on different pilot patterns,considering nonlinear distortion and channel sparsity.The proposed methods achieve sparse channel results by manipulating the least squares(LS)frequency-domain channel estimation results to preserve the most significant taps.The decision-aided method is used to optimize the sparse channel results to reduce the effect of nonlinear distortion.Numerical results show that the channel estimation performance of the proposed methods is better than that of the conventional methods under different pilot patterns.In addition,the bit error rate performance in communication and passive radar detection performance show that the proposed methods have good comprehensive performance.

Voltage/Current-Mode Multifunction Filters Using One Current Feedback Amplifier and Grounded Capacitors

One configuration for realizing voltage-mode multifunction filters and another configuration for realizing current-mode multifunction filters using current feedback amplifiers (CFAs) are presented. The proposed voltage-mode circuit exhibit simultaneously lowpass and bandpass filters. The proposed current-mode circuit exhibit simultaneously lowpass, bandpass and highpass filters. The proposed circuits offer the following features: no requirements for component matching conditions;low active and passive sensitivities;employing only grounded capacitors and the ability to obtain multifunction filters from the same circuit configuration.

Cache Memory Design for Single Bit Architecture with Different Sense Amplifiers

Most modern microprocessors have one or two levels of on-chip caches to make things run faster,but this is not always the case.Most of the time,these caches are made of static random access memory cells.They take up a lot of space on the chip and use a lot of electricity.A lot of the time,low power is more important than several aspects.This is true for phones and tablets.Cache memory design for single bit architecture consists of six transistors static random access memory cell,a circuit of write driver,and sense amplifiers(such as voltage differential sense amplifier,current differential sense amplifier,charge transfer differential sense amplifier,voltage latch sense amplifier,and current latch sense amplifier,all of which are compared on different resistance values in terms of a number of transistors,delay in sensing and consumption of power.The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34μW of power which shows that power is reduced up to 83%,77.75%reduction in the case of the current differential sense amplifier,39.62%in case of charge transfer differential sense amplifier and 50%in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture.Furthermore,power reduction techniques are applied over different blocks of cache memory architecture to optimize energy.The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078μW of power,i.e.,reduce 28%more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.

A VERSATILE CURRENT-MODE BIQUAD USING OPERATIONAL AMPLIFIERS

A versatile current-mode biquadratic filter using three operational amplifiers and nine passive elements is proposed. By suitably choosing the output branch, lowpass, bandpass, highpass, bandstop and allpass transfer functions are realized simultaneously without changing the circuit configuration and elements. Two circuits, one is for low frequency application and the other for high frequency, are proposed. The center frequency, quality factor and gain constants of the circuit can be tuned independently. Simulated results show that the circuits work successfully.

Design and Implement of Low Power Consumption SRAM Based on Single Port Sense Amplifier in 65 nm

With the rapid development of integrated circuits [1], low power consumption has become a constant pursuiting goal of the designer in chip design. As the memory almost takes up the area of the chip, reducing memory power consumption will significantly reduce the overall power consumption of the chip;according to ISSCC’s 2014 report about technology trends discussions, there two points of the super-low power SRAM design: 1) design a more effective static and dynamic power control circuit for each key module of SRAM;2) ensure that in the case of the very low VDD min, SRAM can operating reliably and stably. This paper makes full use reliable of 8T cell, and the single-port sense amplifier has solved problems in the traditional 8T cell structure, making the new structure of the memory at a greater depth still maintain good performance and lower power consumption. Compared with the designed SRAM the SRAM generated by commercial compiler, as the performance loss at SS corner does not exceed 10%, the whole power consumption could be reduced by 54.2%, which can achieve a very good effect of low-power design.

VELAN: Variable Energy Aware Sense Amplifier Link for Asynchronous Network on Chip

A real time multiprocessor chip paradigm is also called a Network-on-Chip (NoC) which offers a promising architecture for future systems-on-chips. Even though a lot of Double Tail Sense Amplifiers (DTSA) are used in architectural approach, the conventional DTSA with transceiver exhibits a difficulty of consuming more energy and latency than its intended design during heavy traffic condition. Variable Energy aware sense amplifier Link for Asynchronous NoC (VELAN) is designed in this research to eliminate the difficulty, which is the combination of Variable DTSA circuitry (V-DTSA) and Transceiver. The V-DTSA circuitry has following components such as bootable DTSA (B-DTSA) and bootable clock gating DTSA (BCG-DTSA), Graph theory based Traffic Estimator (GTE) and controller. Depending upon the traffic rate, the controller activates necessary DTSA modules and transfers information to the receiver. The proposed VELAN design is evaluated on TSMC 90 nm technology, showing 6.157 Gb/s data rate, 0.27 w total link power and 354 ps latency for single stage operation.

Capacitance Sensing and Software-Realized Lock-in Amplifier for the Electromagnetically Levitated Micro Gyroscope

In the novel prototype of micro-gyroscope structure,the new configured capacitance sensing scheme for the micro gyroscope was analyzed and the virtual instrument based detection scheme was implemented.The digital lock-in amplifier was employed in the capacitance detection to restrain the noise interference.The capacitance analysis shows that 1 fF capacitance variation corresponds to 0.1 degree of the turn angle.The differential capacitance bridge and the charge integral amplifier were used as the front signal input interface.In the implementation of digital lock-in amplifier,a new routine which warranted the exactly matching of the reference phase to signal phase was proposed.The result of the experiment shows that digital lock-in amplifier can greatly eliminate the noise in the output signal.The non linearity of the turn angle output is 2.3% and the minimum resolution of turn angle is 0.04 degrees.The application of the software demodulation in the signal detection of micro-electro-mechanical-system(MEMS)device is a new attempt,and it shows the prospective for a high-performance application.

THE DESIGN OF ACTIVE CURRENT-MODE FILTER WITH STATE VARIABLE METHOD

Basing on the state variable method, a block diagram of the current-mode biquad active circuit was proposed, whose integrators were realized using three kinds of active elements such as operational amplifier, second generation current conveyors and operational transconduc-tance amplifiers-electric capacity. The characteristics of each circuit were analyzed.

DOCCII-based electronically tunable current-mode biquadratic filters

A complete state variable current-mode biquadratic filter built by duo-output CCII (DOCCII) with variable current gain is presented. All the coefficients of the filter can be independently tuned through the variable current gain factors of the DOCCII. Based on the principles upon which the general biquadratic filter was constructed, a universal electronically tunable current-mode filter is proposed which implements the low-pass, high-pass, band-pass, band-suppress and all-pass second order transfer functions simultaneously. The PSPICE simulations of frequency responses of second-order filter of are also given.

Realization of a New Current Mode Second-Order Biquad Using Two Current Follower Transconductance Amplifiers (CFTAs)

A new circuit for realization of universal current-mode filter using current Follower Transconductance Amplifiers (CFTAs) is presented. The proposed circuit realizes current-mode low pass, high pass and band pass filter functions simultaneously with a single current source at the input. The band reject and all pass filters can also be obtained from the proposed circuit without any extra hardware. The proposed circuit employs three passive grounded elements and two CFTAs. Linear electronic control of natural frequency ω0 is available in the proposed circuit. The quality factor can be independently adjusted through grounded resistor. The proposed circuit employs two grounded capacitors and a grounded resistor along with two CFTAs. The grounded resistor can be replaced by an OTA based circuit for linear electronic control of quality factor Q0. The circuit exhibits low active and passive sensitivities for ω0 and Q0. Simulation results are obtained using PSPICE software which is in conformity with the theoretical findings.

基于SOA光纤环形激光器的分布式声传感系统

为了降低传统分布式声学传感器(DAS)系统复杂度并提高信噪比(SNR),提出了一种基于半导体光放大器的光纤环形激光器(SOA-FRL)的DAS系统。该系统用SOA-FRL取代了传统的DAS系统中的窄线宽激光器和脉冲调制器,实现了高稳定的光脉冲输出;采用双脉冲外差探测方法,实现了精确的声信号探测和声源定位。实验结果表明:在频率为1 kHz、幅值为1.14 rad的声信号作用下,所提系统的解调SNR高达38.25 dB,空间分辨率为12 m。

一种高速高集成度MaskROM的设计与研究

MaskROM在MCU设计应用中扮演着重要角色,而高速、高集成度是未来发展趋势。设计了一种混合结构MaskROM,兼有NAND的高集成度以及NOR的快速读出优点。子模块中串联的管子越多,集成度越高,但速度会降低。通过对行译码进行小的子模块划分,阵列被划分为多个子模块并联。选择每个子模块为5个MOS管串联,这样既能提高集成度又能保持快速读出的特点。在选中的子模块中,被进一步选中的WL(Word Line)为低,其他WL为高,串联的bit被导通的MOS管短路掉4行,WL为低的那一行MOS管关闭,从而其MOS管两端有没有被金属短接决定了cell是否产生电流。行译码的方式可以很容易地通过数学公式进行归纳和理解。SA采用伪差分方式,通过预设offset方式实现cell的快速读出。基于0.18μm 2P5M EEPROM工艺设计实现了一款32 K×34bit的MaskROM,芯片测试结果表明,在典型条件下其读出速度能达到170 MHz。

应用于忆阻器阵列存内计算的低延时低能耗新型感知放大器

存内计算(Computing In Memory,CIM)在人工智能神经网络的卷积运算方面具有巨大的应用潜力。基于忆阻器阵列的多位存内计算由于具备写入速度快、与互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)工艺兼容等特点,有望成为解决“内存墙”的有效手段。然而,当前多位存内计算电路架构面临输出延时高和能耗大的问题,主要原因为传统感知放大器的性能制约,为此本文提出了一种低延时低能耗多位电流型感知放大器(Low-delay Low-power Multi-bit Current-mode Sense Amplifier,LLM-CSA),通过减少传统CSA电路工作状态数量、简化工作时序来优化功能;采用新型低位检测模块的电路设计思路,来多层次系统性地降低输出延时并优化能耗。使用中芯国际40 nm低漏电逻辑工艺(SMIC40 nm LL),利用Cadence电路设计平台,仿真验证所提LLM-CSA的功能和延时-能耗性能。通过对比分析发现:LLM-CSA比传统CSA输出延时降低1.42倍,能量消耗降低1.56倍。进一步地,以一种4 bit输入、4 bit权重、11 bit输出的忆阻器阵列多位存内计算架构为应用,对比验证所提LLM-CSA的性能:与基于传统CSA的存内计算系统相比,新架构延时降低1.18倍,能耗降低1.03倍。LLM-CSA的提出对促进感知放大器设计思路和忆阻器阵列存内计算架构的发展,具有一定的理论和现实意义。

功率MOS开关的高精度电流检测电路设计

随着军工设备、工业控制、智能汽车等领域的发展,功率MOS开关驱动器的需求量不断提升,其可靠性、安全性等性能要求也在逐步提高。为保证功率MOS管在安全电流下工作,设计了一款高精度高边电流检测电路。利用复合式斩波放大器,大幅降低失调电压对电流采样精度的影响,并保证电路系统有足够的响应速度。该电路采用CSMC 0.18μm高压BCD工艺进行设计,在添加10mV的输入失调电压后,测量精度依然可以达到99%,带宽达到3MHz。

基于阻变存储器的物理不可克隆函数设计

物理不可克隆函数(PUF)将集成电路制造过程中产生的工艺变化作为一种安全原语,已被广泛应用于硬件安全领域,特别是身份认证和密钥存储。提出了一种基于阻变存储器(RRAM)阵列的PUF优化设计,采用2T2R差分存储结构,并利用阵列中RRAM单元的阻值变化产生PUF的随机性,以实现更高安全级别所需的大量激励-响应对(CRP)。RRAM PUF的存储单元基于28 nm工艺实现,其面积仅为0.125μm~2,相比传统PUF存储单元面积开销减小,在入侵和侧信道攻击方面具有更好的鲁棒性。实验数据表明,RRAM PUF唯一性达到了约49.78%,片内汉明距离为0%,一致性良好,具有较好的随机性。

基于电液比例和负载敏感技术的非公路矿用自卸车线控液压转向系统

提出了一种基于电液比例技术和负载敏感技术的兼容有人驾驶和无人驾驶转向功能的大流量和中小流量液压转向系统,分别阐述了两种系统的组成、液压原理和控制方法,为各流量需求的兼容有人驾驶和无人驾驶转向功能的非公路矿用自卸车液压转向系统的设计提供了一种原理方案。

A new low-voltage and high-speed sense amplifier for flash memory

A new low-voltage and high-speed sense amplifier is presented, based on a very simple direct currentmode comparison. It adopts low-voltage reference current extraction and a dynamic output method to realize its performance indicators such as low voltage, low power and high precision. The proposed amplifier can sense a 0.5 #A current gap and work with a lowest voltage of 1 V. In addition, the current power of a single amplifier is optimized by 15%.

A low-voltage sense amplifier for high-performance embedded flash memory

This paper presents a sense amplifier scheme for low-voltage embedded flash （eFlash） memory applications. The topology of the sense amplifier is based on current mode comparison. Moreover, an offset-voltage elimination technique is employed to improve the sensing performance under a small memory cell current. The proposed sense amplifier is designed based on a GSMC 130 nm eFlash process, and the sense time is 0.43 ns at 1.5 V, corresponding to a 46% improvement over the conventional technologies.

Design of an 8 bit differential paired eFuse OTP memory IP reducing sensing resistance

For the conventional single-ended eFuse cell, sensing failures can occur due to a variation of a post-program eFuse resistance during the data retention time and a relatively high program resistance of several kilo ohms. A differential paired eFuse cell is designed which is about half the size smaller in sensing resistance of a programmed eFuse link than the conventional single-ended eFuse cell. Also, a sensing circuit of sense amplifier is proposed, based on D flip-flop structure to implement a simple sensing circuit. Furthermore, a sensing margin test circuit is proposed with variable pull-up loads out of consideration for resistance variation of a programmed eFuse. When an 8 bit eFuse OTP IP is designed with 0.18 ~tm standard CMOS logic of TSMC, the layout dimensions are 229.04 μm ×100.15μm. All the chips function successfully when 20 test chips are tested with a program voltage of 4.2 V.

A low-voltage sense amplifier with two-stage operational amplifier clamping for flash memory

A low-voltage sense amplifier with reference current generator utilizing two-stage operational amplifier clamp structure for flash memory is presented in this paper,capable of operating with minimum supply voltage at1 V.A new reference current generation circuit composed of a reference cell and a two-stage operational amplifier clamping the drain pole of the reference cell is used to generate the reference current,which avoids the threshold limitation caused by current mirror transistor in the traditional sense amplifier.A novel reference voltage generation circuit using dummy bit-line structure without pull-down current is also adopted,which not only improves the sense window enhancing read precision but also saves power consumption.The sense amplifier was implemented in a flash realized in 90 run flash technology.Experimental results show the access time is 14.7 ns with power supply of 1.2 V and slow corner at 125℃.