The present work deals with 12-bit Nyquist current-steering CMOS digital-to-analog converter (DAC) which is an essential part in baseband section of wireless transmitter circuits. Using oversampling ratio (OSR) for th...The present work deals with 12-bit Nyquist current-steering CMOS digital-to-analog converter (DAC) which is an essential part in baseband section of wireless transmitter circuits. Using oversampling ratio (OSR) for the proposed DAC leads to avoid use of an active analog reconstruction filter. The optimum segmentation (75%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher performance is achieved using a new 3-D thermometer decoding method which reduces the area, power consumption and the number of control signals of the digital section. Using two digital channels in parallel, helps reach 1-GSample/s frequency. Simulation results show that the spurious- free-dynamic-range (SFDR) in Nyquist rate is better than 64 dB for sampling frequency up to 1-GSample/s. The analog voltage supply is 3.3 V while the digital part of the chip operates with only 2.4 V. Total power consumption in Nyquist rate measurement is 144.9 mW. The chip has been processed in a standard 0.35 μm CMOS technology. Active area of chip is 1.37 mm2.展开更多
This paper presents an 11-bit 160 MS/s 2-channel current-steering digital-to-analog converter（DAC）IP. The circuit and layout are carefully designed to optimize its performance and area. A 6-2-3 segmented structure i...This paper presents an 11-bit 160 MS/s 2-channel current-steering digital-to-analog converter（DAC）IP. The circuit and layout are carefully designed to optimize its performance and area. A 6-2-3 segmented structure is used for the trade-off among linearity, area and layout complexity. The sizes of current source transistors are calculated out according to the process matching parameter. The unary current cells are placed in a one-dimension distribution to simplify the layout routing, spare area and wiring layer. Their sequences are also carefully designed to reduce integral nonlinearity. The test result presents an SFDR of 72 dBc at 4.88 MHz input signal with DNL ≤60.25 LSB, INL ≤6 0.8 LSB. The full-scale output current is 5 m A with a 2.5 V analog power supply. The core of each channel occupies 0.08 mm^2 in a 1P-8M 55 nm CMOS process.展开更多
为标定光交叉芯片驱动电压,控制光交叉芯片实现光路由功能,提出并搭建了基于多通道DAC(Digital to Analog Converter)阵列的控制驱动电路系统。系统主要由控制系统模块、多路驱动电路模块及上位机控制模块构成。控制电路和驱动电路具有...为标定光交叉芯片驱动电压,控制光交叉芯片实现光路由功能,提出并搭建了基于多通道DAC(Digital to Analog Converter)阵列的控制驱动电路系统。系统主要由控制系统模块、多路驱动电路模块及上位机控制模块构成。控制电路和驱动电路具有调校简单、可双极性输出、输出路数多、加电精确度较高的特点,解决了当前驱动电路工作繁琐、加电极性单一、加电路数少、精度差的问题。上位机控制模块除了可控制驱动电路施加控制电压外,还可接收来自数据采集装置采集到的光功率信号作为控制驱动系统的反馈信号。通过分析控制电压与光功率之间的关系,可得到最佳的光交叉芯片控制驱动电压。系统测试实验结果表明,该系统能提供高精确度的双极性驱动电压,有效地对光交叉芯片进行驱动。可在较短的时间内标定出光开关的控制电压,完全可以满足有源光交叉芯片控制中对驱动电压的需求。该系统在光交叉芯片控制方面具有一定的应用价值。展开更多
A high-speed SiGe BiCMOS direct digital frequency synthesizer（DDS）is presented.The design integrates a high-speed digital DDS core,a high-speed differential current-steering mode 10-bit D/A converter,a serial/parall...A high-speed SiGe BiCMOS direct digital frequency synthesizer（DDS）is presented.The design integrates a high-speed digital DDS core,a high-speed differential current-steering mode 10-bit D/A converter,a serial/parallel interface,and clock control logic.The DDS design is processed in 0.35μm SiGe BiCMOS standard process technology and worked at 1 GHz system frequency.The measured results show that the DDS is capable of generating a frequency-agile analog output sine wave up to 400＋MHz.展开更多
A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed. The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in na...A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed. The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-CMOS design. The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains. The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB. The measured SFDR at 1.7 MHz output signal is 58.91 dB, 58.53 dB and 56.98 dB for R/G/B channels, respectively. The DAC has good static and dynamic performance despite the single-ended output. The average rising time and falling time of three channels are 0.674 ns and 0.807 ns. The analog/digital power supply is 3.3 V/1.1 V. This triple-channel DAC occupies 0.5656 mm^2.展开更多
电子设备集成度的提高对于音频集成电路生产和测试等环节的要求越来越高,尤其是音频数模转换器(Digital to Analog Converter,DAC),本质上为数模混合信号电路,采用数模混合信号自动化测试设备(Automatic Test Equipment,ATE)价格昂贵,...电子设备集成度的提高对于音频集成电路生产和测试等环节的要求越来越高,尤其是音频数模转换器(Digital to Analog Converter,DAC),本质上为数模混合信号电路,采用数模混合信号自动化测试设备(Automatic Test Equipment,ATE)价格昂贵,而采用传统自动测试仪测试覆盖率低、测试时间长,导致这类电路的测试成本较高且测试产能不足。介绍了一种基于现场可编程门阵列(Field Programmable Gate Array,FPGA)和LabWindows的音频DAC电路测试方案,硬件上用FPGA实现音频测试所需的直接数字频率合成(Direct Digital Frequency Synthesizers,DDFS)模块,软件上通过运用LabWindows自带的采样、加窗、快速傅里叶变换(Fast Fourier Transform,FFT)等数字信号处理函数,快速准确地测试各项模拟参数,并在用户界面(User Interface,UI)显示测试值和后台保存测试数据。展开更多
品牌简介德国B.M.C Audio奔玛仕是由在业界知名的德国资深音响设计师Carlos Candeias于2009年在德国Hessian州Kassel市成立,他把数十年来在技术及音乐方面的经验与追求放进产品中。B.M.C品牌的英文Balanced Music Concept是全平衡音乐...品牌简介德国B.M.C Audio奔玛仕是由在业界知名的德国资深音响设计师Carlos Candeias于2009年在德国Hessian州Kassel市成立,他把数十年来在技术及音乐方面的经验与追求放进产品中。B.M.C品牌的英文Balanced Music Concept是全平衡音乐的意思,而B.M.C.产品的模拟电路也全部采取全平衡设计,是真正对称的平衡设计。展开更多
文摘The present work deals with 12-bit Nyquist current-steering CMOS digital-to-analog converter (DAC) which is an essential part in baseband section of wireless transmitter circuits. Using oversampling ratio (OSR) for the proposed DAC leads to avoid use of an active analog reconstruction filter. The optimum segmentation (75%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher performance is achieved using a new 3-D thermometer decoding method which reduces the area, power consumption and the number of control signals of the digital section. Using two digital channels in parallel, helps reach 1-GSample/s frequency. Simulation results show that the spurious- free-dynamic-range (SFDR) in Nyquist rate is better than 64 dB for sampling frequency up to 1-GSample/s. The analog voltage supply is 3.3 V while the digital part of the chip operates with only 2.4 V. Total power consumption in Nyquist rate measurement is 144.9 mW. The chip has been processed in a standard 0.35 μm CMOS technology. Active area of chip is 1.37 mm2.
基金supported by the Major National Science&Technology Program of China(No.2012ZX03004004-002)
文摘This paper presents an 11-bit 160 MS/s 2-channel current-steering digital-to-analog converter（DAC）IP. The circuit and layout are carefully designed to optimize its performance and area. A 6-2-3 segmented structure is used for the trade-off among linearity, area and layout complexity. The sizes of current source transistors are calculated out according to the process matching parameter. The unary current cells are placed in a one-dimension distribution to simplify the layout routing, spare area and wiring layer. Their sequences are also carefully designed to reduce integral nonlinearity. The test result presents an SFDR of 72 dBc at 4.88 MHz input signal with DNL ≤60.25 LSB, INL ≤6 0.8 LSB. The full-scale output current is 5 m A with a 2.5 V analog power supply. The core of each channel occupies 0.08 mm^2 in a 1P-8M 55 nm CMOS process.
文摘为标定光交叉芯片驱动电压,控制光交叉芯片实现光路由功能,提出并搭建了基于多通道DAC(Digital to Analog Converter)阵列的控制驱动电路系统。系统主要由控制系统模块、多路驱动电路模块及上位机控制模块构成。控制电路和驱动电路具有调校简单、可双极性输出、输出路数多、加电精确度较高的特点,解决了当前驱动电路工作繁琐、加电极性单一、加电路数少、精度差的问题。上位机控制模块除了可控制驱动电路施加控制电压外,还可接收来自数据采集装置采集到的光功率信号作为控制驱动系统的反馈信号。通过分析控制电压与光功率之间的关系,可得到最佳的光交叉芯片控制驱动电压。系统测试实验结果表明,该系统能提供高精确度的双极性驱动电压,有效地对光交叉芯片进行驱动。可在较短的时间内标定出光开关的控制电压,完全可以满足有源光交叉芯片控制中对驱动电压的需求。该系统在光交叉芯片控制方面具有一定的应用价值。
基金supported by the National Natural Science Foundation of China(Nos.60773025,60906009)the Program for Changjiang Scholars and Innovative Research Team in University
文摘A high-speed SiGe BiCMOS direct digital frequency synthesizer（DDS）is presented.The design integrates a high-speed digital DDS core,a high-speed differential current-steering mode 10-bit D/A converter,a serial/parallel interface,and clock control logic.The DDS design is processed in 0.35μm SiGe BiCMOS standard process technology and worked at 1 GHz system frequency.The measured results show that the DDS is capable of generating a frequency-agile analog output sine wave up to 400＋MHz.
文摘A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed. The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-CMOS design. The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains. The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB. The measured SFDR at 1.7 MHz output signal is 58.91 dB, 58.53 dB and 56.98 dB for R/G/B channels, respectively. The DAC has good static and dynamic performance despite the single-ended output. The average rising time and falling time of three channels are 0.674 ns and 0.807 ns. The analog/digital power supply is 3.3 V/1.1 V. This triple-channel DAC occupies 0.5656 mm^2.
文摘电子设备集成度的提高对于音频集成电路生产和测试等环节的要求越来越高,尤其是音频数模转换器(Digital to Analog Converter,DAC),本质上为数模混合信号电路,采用数模混合信号自动化测试设备(Automatic Test Equipment,ATE)价格昂贵,而采用传统自动测试仪测试覆盖率低、测试时间长,导致这类电路的测试成本较高且测试产能不足。介绍了一种基于现场可编程门阵列(Field Programmable Gate Array,FPGA)和LabWindows的音频DAC电路测试方案,硬件上用FPGA实现音频测试所需的直接数字频率合成(Direct Digital Frequency Synthesizers,DDFS)模块,软件上通过运用LabWindows自带的采样、加窗、快速傅里叶变换(Fast Fourier Transform,FFT)等数字信号处理函数,快速准确地测试各项模拟参数,并在用户界面(User Interface,UI)显示测试值和后台保存测试数据。
文摘品牌简介德国B.M.C Audio奔玛仕是由在业界知名的德国资深音响设计师Carlos Candeias于2009年在德国Hessian州Kassel市成立,他把数十年来在技术及音乐方面的经验与追求放进产品中。B.M.C品牌的英文Balanced Music Concept是全平衡音乐的意思,而B.M.C.产品的模拟电路也全部采取全平衡设计,是真正对称的平衡设计。
