This paper presents a high-speed column-parallel cyclic analog-to-digital converter（ADC） for a CMOS image sensor.A correlated double sampling（CDS） circuit is integrated in the ADC,which avoids a stand-alone CDS ci...This paper presents a high-speed column-parallel cyclic analog-to-digital converter（ADC） for a CMOS image sensor.A correlated double sampling（CDS） circuit is integrated in the ADC,which avoids a stand-alone CDS circuit block.An offset cancellation technique is also introduced,which reduces the column fixed-pattern noise（FPN） effectively.One single channel ADC with an area less than 0.02 mm^2 was implemented in a 0.13μm CMOS image sensor process.The resolution of the proposed ADC is 10-bit,and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively.The power consumption from 3.3 V supply is only 0.66 mW.An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels.The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.展开更多
A readout integrated circuit （ROIC） for a MEMS （microelectromechanical system）-array-based focal plane （MAFP） intended for imaging applications is presented. The ROIC incorporates current sources for diode de- t...A readout integrated circuit （ROIC） for a MEMS （microelectromechanical system）-array-based focal plane （MAFP） intended for imaging applications is presented. The ROIC incorporates current sources for diode de- tectors, scanners, timing sequence controllers, differential buffered injection-capacitive trans-impedance amplifier （DBI-CTIA） and 10-bit cyclic ADCs, and is integrated with MAFP using 3-D integration technology. A small-signal equivalent model is built to include thermal detectors into circuit simulations. The biasing current is optimized in terms of signal-to-noise ratio and power consumption. Layout design is tailored to fulfill the requirements of 3-D integration and to adapt to the size of MAFP elements, with not all but only the 2 bottom metal layers to complete nearly all the interconnections in DBI-CTIA and ADC in a 40/zm wide column. Experimental chips are designed and fabricated in a 0.35 μm CMOS mixed signal process, and verified in a code density test of which the results indicate a （0.29/-0.31） LSB differential nonlinearity （DNL） and a （0.61/-0.45） LSB integral nonlinearity （INL）. Spectrum analysis shows that the effective number of bits （ENOB） is 9.09. The RO1C consumes 248 mW of power at most if not to cut off quiescent current paths when not needed.展开更多
A high linearity,undersampling 14-bit 357 kSps cyclic analog-to-digital convert（ADC） is designed for a radio frequency identification transceiver system.The passive capacitor error-average（PCEA） technique is adopt...A high linearity,undersampling 14-bit 357 kSps cyclic analog-to-digital convert（ADC） is designed for a radio frequency identification transceiver system.The passive capacitor error-average（PCEA） technique is adopted for high accuracy.An improved PCEA sampling network,capable of eliminating the crosstalk path of two pipelined stages,is employed.Opamp sharing and the removal of the front-end sample and hold amplifier are utilized for low power dissipation and small chip area.An additional digital calibration block is added to compensate for the error due to defective layout design.The presented ADC is fabricated in a 180 nm CMOS process,occupying 0.65×1.6 mm^2. The input of the undersampling ADC achieves 15.5 MHz with more than 90 dB spurious free dynamic range（SFDR）, and the peak SFDR is as high as 106.4 dB with 2.431 MHz input.展开更多
A low power 10-bit 250-k sample per second （KSPS） cyclic analog to digital converter （ADC） is presented. The ADC＇s offset errors are successfully cancelled out through the proper choice of a capacitor switching s...A low power 10-bit 250-k sample per second （KSPS） cyclic analog to digital converter （ADC） is presented. The ADC＇s offset errors are successfully cancelled out through the proper choice of a capacitor switching sequence. The improved redundant signed digit algorithm used in the ADC can tolerate high levels of the comparator＇s offset errors and switched capacitor mismatch errors. With this structure, it has the advantages of simple circuit configuration, small chip area and low power dissipation. The cyclic ADC manufactured with the Chartered 0.35 μm 2P4M process shows a 58.5 dB signal to noise and distortion ratio and a 9.4 bit effective number of bits at a 250 KSPS sample rate. It dissipates 0.72 mW with a 3.3 V power supply and occupies dimensions of 0.42 × 0.68 mm2.展开更多
基金supported by the National Natural Science Foundation of China(Nos.60976023,61234003)the Special Funds for Major State Basic Research Project of China(No.2011CB932902)
文摘This paper presents a high-speed column-parallel cyclic analog-to-digital converter（ADC） for a CMOS image sensor.A correlated double sampling（CDS） circuit is integrated in the ADC,which avoids a stand-alone CDS circuit block.An offset cancellation technique is also introduced,which reduces the column fixed-pattern noise（FPN） effectively.One single channel ADC with an area less than 0.02 mm^2 was implemented in a 0.13μm CMOS image sensor process.The resolution of the proposed ADC is 10-bit,and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively.The power consumption from 3.3 V supply is only 0.66 mW.An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels.The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.
基金Project supported by by National Natural Science Foundation of China(No.61271130)the Beijing Municipal Science and Tech Project(No.D13110100290000)+1 种基金the Tsinghua University Initiative Scientific Research Program(No.20131089225)the Shenzhen Science and Technology Development Fund(No.CXZZ20130322170740736)
文摘A readout integrated circuit （ROIC） for a MEMS （microelectromechanical system）-array-based focal plane （MAFP） intended for imaging applications is presented. The ROIC incorporates current sources for diode de- tectors, scanners, timing sequence controllers, differential buffered injection-capacitive trans-impedance amplifier （DBI-CTIA） and 10-bit cyclic ADCs, and is integrated with MAFP using 3-D integration technology. A small-signal equivalent model is built to include thermal detectors into circuit simulations. The biasing current is optimized in terms of signal-to-noise ratio and power consumption. Layout design is tailored to fulfill the requirements of 3-D integration and to adapt to the size of MAFP elements, with not all but only the 2 bottom metal layers to complete nearly all the interconnections in DBI-CTIA and ADC in a 40/zm wide column. Experimental chips are designed and fabricated in a 0.35 μm CMOS mixed signal process, and verified in a code density test of which the results indicate a （0.29/-0.31） LSB differential nonlinearity （DNL） and a （0.61/-0.45） LSB integral nonlinearity （INL）. Spectrum analysis shows that the effective number of bits （ENOB） is 9.09. The RO1C consumes 248 mW of power at most if not to cut off quiescent current paths when not needed.
基金supported by the National High Technology Research and Development Program of China(No.2006AA04A109)
文摘A high linearity,undersampling 14-bit 357 kSps cyclic analog-to-digital convert（ADC） is designed for a radio frequency identification transceiver system.The passive capacitor error-average（PCEA） technique is adopted for high accuracy.An improved PCEA sampling network,capable of eliminating the crosstalk path of two pipelined stages,is employed.Opamp sharing and the removal of the front-end sample and hold amplifier are utilized for low power dissipation and small chip area.An additional digital calibration block is added to compensate for the error due to defective layout design.The presented ADC is fabricated in a 180 nm CMOS process,occupying 0.65×1.6 mm^2. The input of the undersampling ADC achieves 15.5 MHz with more than 90 dB spurious free dynamic range（SFDR）, and the peak SFDR is as high as 106.4 dB with 2.431 MHz input.
基金Project supposed by the Science and Technology Program of Tianjin,China(No.08ZCKFGX00200)
文摘A low power 10-bit 250-k sample per second （KSPS） cyclic analog to digital converter （ADC） is presented. The ADC＇s offset errors are successfully cancelled out through the proper choice of a capacitor switching sequence. The improved redundant signed digit algorithm used in the ADC can tolerate high levels of the comparator＇s offset errors and switched capacitor mismatch errors. With this structure, it has the advantages of simple circuit configuration, small chip area and low power dissipation. The cyclic ADC manufactured with the Chartered 0.35 μm 2P4M process shows a 58.5 dB signal to noise and distortion ratio and a 9.4 bit effective number of bits at a 250 KSPS sample rate. It dissipates 0.72 mW with a 3.3 V power supply and occupies dimensions of 0.42 × 0.68 mm2.
