Efficient Early Termination Strategy for LDPC Codes in GPS Systems

By exploiting the structural features of L1C messages,a novel Early Termination( ET) strategy is proposed to speed up the decoding of low-density parity-check( LDPC) codes in the GPS system. The proposed strategy is based on the cyclic redundancy check( CRC) of the messages in the subframes 2 and 3. The simulation results show that average number of iterations of the proposed strategy is less than that of the standard ET strategy,with nearly no degradation in decoding performance. Besides,the proposed ET strategy can be efficiently implemented in a sequential or parallel manner. Thus,the proposed ET strategy is attractive for practical purposes.

JOINT LLR-CRC ERROR MITIGATION FOR TWO-WAY ADAPTIVE DENOISE-AND-FORWARD NETWORK CODING

Network Coding (NC) brings correlation between the coded signals from different sources, which makes the system more vulnerable to the decode error at relay. Conventional Cyclic Redundancy Code (CRC) has been implemented for error bit detection. However, its error correction is simply ignored. To fully exploit this feature, this paper proposes a novel joint Log-Likelihood Ratio (LLR) CRC error mitigation for NC two way relay channel. Specific thresholds are designed to estimate the error number of data block and identify those which can be recovered if the number is within the error correction scope of CRC. We examine two modes of the thresholds, one based on the average Bit Error Rate (BER) of source-relay link, while the other based on that of instantaneous one. We provide the full analysis for the Pair-wise Error Probability (PEP) performance of the scheme. A variety of numerical results are presented to reveal the superiority of the proposed scheme to conventional CRC NC under independent Rayleigh fading channels. Moreover, the efficiencies of the proposed thresholds are also validated.

CRC Look-up Table Optimization for Single-Bit Error Correction

Many communication systems use the cyclic redundancy code （CRC） technique for protecting key data fields from transmission errors by enabling both single-bit error correction and multi-bit error detection. The look-up table design is very important for the error-correction implementation. This paper presents a CRC look-up table optimization method for single-bit error correction. The optimization method minimizes the address length of the pre-designed look-up table while satisfying certain restrictions. The circuit implementation is also presented to show the feasibility of the method in the application specific integrated circuit design. An application of the optimization method in the generic framing procedure protocol is implemented using field programmable gatearrays. The result shows that the memory address length has been minimized, while keeping a very simple circuit implementation.