A stack data cache is designed according to the features of intelligent workstation(IW) in A1 type intelligent network. Its page fault rate is up to 10 -3 , and the overhead of page replacement is only half of th...A stack data cache is designed according to the features of intelligent workstation(IW) in A1 type intelligent network. Its page fault rate is up to 10 -3 , and the overhead of page replacement is only half of the normal. Stack data cache is suitable for IWs inference engine especially.展开更多
Due to continuous decreasing feature size and increasing device density, on-chip caches have been becoming susceptible to single event upsets, which will result in multi-bit soft errors. The increasing rate of multi-b...Due to continuous decreasing feature size and increasing device density, on-chip caches have been becoming susceptible to single event upsets, which will result in multi-bit soft errors. The increasing rate of multi-bit errors could result in high risk of data corruption and even application program crashing. Traditionally, L1 D-caches have been protected from soft errors using simple parity to detect errors, and recover errors by reading correct data from L2 cache, which will induce performance penalty. This work proposes to exploit the redundancy based on the characteristic of data values. In the case of a small data value, the replica is stored in the upper half of the word. The replica of a big data value is stored in a dedicated cache line, which will sacrifice some capacity of the data cache. Experiment results show that the reliability of L1 D-cache has been improved by 65% at the cost of 1% in performance.展开更多
文摘A stack data cache is designed according to the features of intelligent workstation(IW) in A1 type intelligent network. Its page fault rate is up to 10 -3 , and the overhead of page replacement is only half of the normal. Stack data cache is suitable for IWs inference engine especially.
基金Projects(61472322,61272122)supported by the National Natural Science Foundation of ChinaProject(3102014JSJ0001)supported by the Fundamental Research Funds for the Central Universities,China+1 种基金Project(2013JQ8034)supported by the Natural Science Foundation of Shaanxi Province,ChinaProject(JC20120239)supported by the Basic Research Foundation of NWPU,China
文摘Due to continuous decreasing feature size and increasing device density, on-chip caches have been becoming susceptible to single event upsets, which will result in multi-bit soft errors. The increasing rate of multi-bit errors could result in high risk of data corruption and even application program crashing. Traditionally, L1 D-caches have been protected from soft errors using simple parity to detect errors, and recover errors by reading correct data from L2 cache, which will induce performance penalty. This work proposes to exploit the redundancy based on the characteristic of data values. In the case of a small data value, the replica is stored in the upper half of the word. The replica of a big data value is stored in a dedicated cache line, which will sacrifice some capacity of the data cache. Experiment results show that the reliability of L1 D-cache has been improved by 65% at the cost of 1% in performance.
