Low overhead design-for-testability for scan-based delay fault testing

An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generation process complex and produce lower coverage for scan-based designs as compared with non-scan designs, whereas techniques such as enhanced-scan test can make the test easy but need an extra holding latch to add substantial hardware overhead. A new tri-state holding logic is presented to replace the common holding latch in enhanced-scan test to get a substantial low hardware overhead. This scheme can achieve low delay overhead by avoiding the holding latch on the critical timing scan path. What＇s more, this method can also keep the state and signal activity in the combinational circuit from the scan during data scan-in operation to reduce the power dissipation. Experiment results on a set of ISCAS89 benchmarks show the efficiency of the proposed scheme.

Testing Cross-Talk Induced Delay Faults in Digital Circuit Based on Transient Current Analysis

The delay fault induced by cross-talk effect is one of the difficult problems in the fault diagnosis of digital circuit. An intelligent fault diagnosis based on IDDT testing and support vector machines （SVM） classifier was proposed in this paper. Firstly, the fault model induced by cross-talk effect and the IDDT testing method were analyzed, and then a delay fault localization method based on SVM was presented. The fault features of the sampled signals were extracted by wavelet packet decomposition and served as input parameters of SVM classifier to classify the different fault types. The simulation results illustrate that the method presented is accurate and effective, reaches a high diagnosis rate above 95%.

A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults

A new classification of path-delay fault testability in a combinational circuit is presented in terms of testability of stuck-at faults in an equivalent circuit. Earlier results describing correlation of path-delay and stuck-at faults are either incomplete, or use a complex model of equivalent circuit based on timing parameters. It is shown here that a path-delay fault (rising or falling) is testable if and only if certain single or multiple stuck-at fault in the equivalent circuit is testable. Thus, all aspects of path-delay faults related to testability under various classification schemes can be interpreted using the stuck-at fault model alone. The results unify most of the existing concepts and provide a better understanding of path-delay faults in logic circuits. Keywords delay fault - false path - redundancy - stuck-at fault Regular PaperThis work was funded in part by Motorola India Electronics Ltd., Bangalore 560042, India.An earlier version of this paper appeared in the Proceedings of the 12th Int. Coaf. VLSI Design, Jan. 1999.Subhashis Majumder is a professor and course leader for the Computer Science and Engineering Department of International Institute of Information Technology, Kolkata. He started his career in Texas Instruments India Pvt. Ltd. and has over seven years of industry experience. He received his M. Tech degree in computer science from the Indian Statistical Institute, Kolkata in 1996. His undergraduate work was done in the Electronics and Telecommunication Engineering Dept. of the Jadvpur University, Koikata. He also worked as a research assistant in the Computer Eng. Dept. of Rutgers University for a year. He has led product development teams working on protocol stack development as well as VoIP. His current areas of interest include delay fault testing, wire routing, partitioning, approximation algorithms, and application of computational geometry to CAD problems.Bhargab B. Bhattacharya received the B.Sc. degree in physics from the Presidency College, Calcutta, the B.Tech. and M.Tech. degrees in radiophysics and electronics, and the Ph.D. degree in computer science all from the University of Calcutta, India. Since 1982, he has been on the faculty of the Indian Statistical Institute, Calcutta, where currently he is a full professor. He visited the Department of Computer Science and Engineering, University of Nebraska-Lincoln, USA, during 1985–1987, and 2001–2002, and the Fault-Tolerant Computing Group, Institute of Informatics, at the University of Potsdam, Germany during 1998–2000. His research interest includes logic synthesis and testing of VLSI circuits, physical design, graph algorithms, and image processing architecture. He has published more than 130 papers in archival journals and refereed conference proceedings, and holds 6 United States patents. Currently, he is collaborating with Intel Corporation, USA, and IRISA, France, for development of image processing hardware and reconfigurable parallel computing tools. Dr. Bhattacharya is a fellow of the Indian National Academy of Engineering. He served on the conference committees of the International Test Conference (ITC), the Asian Test Symposium (ATS), the VLSI Design and Test Workshop (VDAT), the International Conference on Advanced Computing (ADCOMP), and the International Conference on High-Performance Computing (HiPC). For the International Conference on VLSI Design, he served as Tutorial Co-Chair (1994), Program Co-Chair (1997), General Co-Chair (2000), and as a member of the Steering Committee during 2001–2003. He is on the editorial board of the Journal of Circuits, Systems, and Computers (World Scientific, Singapore), and the Journal of Electronic Testing: Theory and Applications (Kluwer Academic Publishers, USA). [http://www.isical.ac.in/~bhargab]Vishwani D. Agrawal is the James J. Danaher Professor of Electrical and Computer Engineering at Auburn University, Alabama. He has over thirty years of industry and University experience, working at Bell Labs, Murray Hill, NJ; Rutgers University, New Brunswick, NJ; TRW, Redondo Beach, CA; IIT, Delhi, India; EG&G, Albuquerque. NM; and ATI, Champaign, IL. His areas of work include VLSI testing, lowpower design, and microwave antennas. He obtained his B.E. degree from the University of Roorkee (renamed as Indian Institute of Technology, Roorkee), India, in 1964; M.E. degree from the Indian Institute of Science, Bangalore, India, in 1966; and Ph.D. degree in electrical engineering from the University of Illinois, Urbana-Champaign, in 1971. He has published over 250 papers, has coauthored five books and holds thirteen United States patents. His textbook, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits (Kluwer Academic Publishers), co-authored with M. L. Bushnell, was published in 2000. He is the founder and Editor-in-Chief (1990-) of the Journal of Electronic Testing: Theory and Applications, and a past Editor-in-Chief (1985–87) of the IEEE Design & Test of Computers magazine. He is the Founder and Consulting Editor of the Frontiers in Electronic Testing Book Series of Kluwer Academic Publishers, Boston. He is a co-founder of the International Conference on VLSI Design, and the International Workshops on VLSI Design and Test, held annually in India. He has served on numerous conference committees and is a frequently invited speaker. He was the invited Plenary Speaker at the 1998 International Test Conference, Washington D.C., and the Keynote Speaker at the Ninth Asian Test Symposium in December 2000. During 1989 and 1990, he served on the Board of Governors of the IEEE Computer Society, and in 1994, chaired the Fellow Selection Committee of that Society. He has received seven Best Paper Awards and one Honorable Mention Paper Award. In 1998, he received the Harry H. Goode Memorial Award of the IEEE Computer Society, for innovative contributions to the field of electronic testing, and in 1993, received the Distinguished Alumnus Award of the University of Illinois at Urbana-Champaign, in recognition of his outstanding contributions in design and test of VLSI systems. Dr. Agrawal is a fellow of the IEEE, the ACM, and IETE-India. He has served on the advisory boards of the ECE Departments at University of Illinois, New Jersey Institute of Technology, and the City College of the City University of New York. [http://www.ece.wisc.edu/~va]Michael L. Bushnell is a professor and a Board of Trustees Research Fellow in the Electrical and Computer Engineering Department at Rutgers University, New Jersey. He was also a Henry Rutgers Research Fellow. He has 24 years of industry and university experience, working at General Electric, Honeywell, Instron, Applicon, and Rutgers University. He received his Ph.D. degree in 1986 and his M.S. degree in 1983, both from Carnegie Mellon University. His undergraduate work was done at the Massachusetts Institute of Technology. He is a Presidential Young Investigator (1990) of the National Science Foundation of the United States. He is a co-author of 4 books (including the leading VLSI testing textbook entitled Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits (Kluwer Academic Publishers, 2000), co-authored with Vishwani Agrawal), 91 papers, and 7 patents. He is the co-author of two Prize Papers and one Honorable Mention paper. He served twice as Program Co-Chair of the International Conference on VLSI Design (1995 and 1996), and twice as the Conference Vice-Chair of the North Atlantic Test Workshop (2002 and 2003). His current VLSI CAD research interests are automatic mixed-signal circuit test-pattern generation, built-in self-testing, synthesis for testability, fault modeling for nano-technology, and low-power design. [http://www.ece.rutgers.edu/directory/bushnell.html]

Probabilistic Delay Fault Model for DVFS Circuits

Decreasing the power supply voltage in dynamic voltage frequency scaling to save power con- sumption may introduce extra delays in CMOS circuits, which may cause errors. This paper presents the probabilistic delay fault model （PDFM）, which describes the probability of an error occurring as a function of the power supply voltage and the clock period in synchronous CMOS circuits. In a wide range of applica- tions （graphic, video, digital filtering, etc.）, errors occurring with low probability and not remaining for a long time are acceptable. For combinational circuits which have long critical paths with low probability of excita- tion, a performance increase is achieved with a certain rate of errors determined by the PDFM compared with the traditional design which considers the worst case. The PDFM applied to array multipliers and ripple carry adders shows the agreement of the predicted probabilities with simulated delay histograms to support the practicality of using the PDFM to select power supply voltage and clock period in dynamic voltage fre- quency scaling circuits with tolerable error rates.

H_-/H_∞ fault detection filter design for interval time-varying delays switched systems

The problem of the robust fault detection filter design for time-varying delays switched systems is considered in the framework of mixed H-/H∞. Firstly, the weighted H∞ performance index is utilized as the robustness performance, and the H- index is used as the sensitivity performance for obtaining the robust fault detection filter. Then a novel multiple Lyapunov-Krasovskii function is proposed for deriving sufficient existence conditions of the robust fault detection filter based on the average dwell time technique. By introducing slack matrix variable, the coupling between the Lyapunov matrix and system matrix is removed, and the conservatism of results is reduced. Based on the robust fault detection filter, residual is generated and evaluated for detecting faults. In addition, the results of this paper are dependent on time delays,and represented in the form of linear matrix inequalities. Finally,the simulation example verifies the effectiveness of the proposed method.

An Improved NHPP Model with Time-Varying Fault Removal Delay

In this paper, an improved NHPP model is proposed by replacing constant fault removal time with time-varying fault removal delay in NHPP model, proposed by Daniel R Jeske. In our model, a time-dependent delay function is established to fit the fault removal process. By using two sets of practical data, the descriptive and predictive abilities of the improved NHPP model are compared with those of the NHPP model, G-O model, and delayed S-shape model. The results show that the improved model can fit and predict the data better.

基于故障树的某型航空发动机空中停车故障研究

针对某型飞机更换发动机后试飞时,出现空中停车的特情,对发动机和主燃油泵调节器开展外场检查和返厂检查。基于检查结果和飞参数据,以空中停车为顶事件,从飞机、发动机、进气道和发动机匹配、飞行状态等方面,建立故障树并开展故障排查,确定停车原因为主燃油泵高空慢车状态供油异常。针对高空慢车状态供油异常,结合试验“主燃油泵调节器减速时间异常变化”的结果,以此为顶事件建立故障树。基于液压延迟器工作情况分析故障机理,明确延迟器杆回油小孔不通畅是造成减速时间异常变化的原因。最终,结合飞行条件和故障分析结果,明确停车原因,提出改进建议,对同类型特情排故有一定的参考意义。