2.5Gb/s/ch 0.18μm CMOS Data Recovery Circuit

A 2.5Gb/s/ch data recovery （DR） circuit is designed for an SFI-5 interface. To make the parallel data bit-synchronization and reduce the bit error rate （BER） ,a delay locked loop （DLL） is used to place the center of the data eye exactly at the rising edge of the data-sampling clock. A single channel DR circuit was fabricated in TSMC＇s standard 0. 18μm CMOS process. The chip area is 0. 46mm^2. With a 2^32 - 1 pseudorandom bit sequence （PRBS） input,the RMS jitter of the recovered 2.5Gb/s data is 3.3ps. The sensitivity of the single channel DR is less than 20mV with 10-12 BER.

Multipath tracking with LTE signals for accurate TOA estimation in the application of indoor positioning

Indoor positioning with high accuracy plays an important role in different application scenar-ios.As a widely used mobile communication signal,the Long-Term Evolution(LTE)network can be well received in indoor and outdoor environments.This article studies a method of using different reference signals in the LTE downlink for carrier phase time of arrival(TOA)estimation.Specifically,a solution is proposed and a multipath tracking Software Defined Receiver(SDR)is developed for indoor positioning.With our SDR indoor positioning system,the pilot signals of the LTE signals are firstly obtained by the coarse synchronization and demodulation.Then,with the assistance of the pilot signals,the time delay acquisition,the multipath estimating delay lock loop(MEDLL)algorithm,and the multipath anomaly detection are sequentially carried out to obtain navigation observations of received signals.Furthermore,to compare the perfor-mance of different pilot signals,the Secondary Synchronous Signals(SSS)and Cell Reference Signals(CRS)are used as pilot signals for carrier phase-based TOA estimation,respectively.Finally,to quantify the accuracy of our multipath tracking SDR,indoor field tests are carried out in a conference environment,where an LTE base station is installed for commercial use.Our test results based on CRS show that,in the static test scenarios,the TOA accuracy measured by the 1-σerror interval is about 0.5 m,while in the mobile environment,the probability of range accuracy within 1.0 m is 95%.

A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling

A 10-bit 250-MSPS two-channel time-interleaved charge-domain（CD） pipelined analog-to-digital converter （ADC） is presented.MOS bucket-brigade device（BBD） based CD pipelined architecture is used to achieve low power consumption.An all digital low power DLL is used to alleviate the timing mismatches and to reduce the aperture jitter.A new bootstrapped MOS switch is designed in the sample and hold circuit to enhance the IF sampling capability.The ADC achieves a spurious free dynamic range（SFDR） of 67.1 dB,signal-to-noise ratio （SNDR） of 55.1 dB for a 10.1 MHz input,and SFDR of 61.6 dB,SNDR of 52.6 dB for a 355 MHz input at full sampling rate.Differential nonlinearity（DNL） is ＋0.5/-0.4 LSB and integral nonlineariry（INL） is ＋0.8/-0.75 LSB.Fabricated in a 0.18-μm 1P6M CMOS process,the prototype 10-bit pipelined ADC occupies 1.8×1.3 mm2 of active die area,and consumes only 68 mW at 1.8 V supply.

A 16 b 2 GHz digital-to-analog converter in 0.18 μm CMOS with digital calibration technology

This paper presents a 16-bit 2 GSPS digital-to-analog converter （DAC） in 0.18/zm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input data is received with a two-channel LVDS interface. The DLL technology is introduced to meet the timing requirements between phases of the LVDS data and the data sampling clock. A FIFO is designed to absorb the phase difference between the data clock and DAC system clock. A delay controller is integrated to adjust the phase relationship between the high speed digital clock and analog clock, obtaining a sampling rate of 2 GSPS. The current source mismatch at higher bits is calibrated in the digital domain. Test results show that the DAC achieves 74.02 dBC SFDR at analog output of 36 MHz, and DNL less than ±2.1 LSB ＆ INL less than ±4.3 LSB after the chip is calibrated.