Modular Timing Constraints for Delay-Insensitive Systems

This paper introduces ARCtimer, a framework for modeling, generating, verifying, and enforcing timing constraints for individual self-timed handshake components. The constraints guarantee that the component＇s gate-level circuit implementation obeys the component＇s handshake protocol specification. Because the handshake protocols are delayinsensitive, self-timed systems built using ARCtimer-verified components are also delay-insensitive. By carefully considering time locally, we can ignore time globally. ARCtimer comes early in the design process as part of building a library of verified components for later system use. The library also stores static timing analysis （STA） code to validate and enforce the component＇s constraints in any self-timed system built using the library. The library descriptions of a handshake component＇s circuit, protocol, timing constraints, and STA code are robust to circuit modifications applied later in the design process by technology mapping or layout tools. In addition to presenting new work and discussing related work, this paper identifies critical choices and explains what modular timing verification entails and how it works.

Quasi Delay-Insensitive High Speed Two-Phase Protocol Asynchronous Wrapper for Network on Chips

For the purpose of solving the shortcomings of low speed and high power consumption of asynchronous wrapper in conventional network on chips,this paper proposes a quasi delay-insensitive high-speed two-phase operation mode asynchronous wrapper.The metastable state in sampling data procedure can be avoided by detecting the write/read signal, which can be used to stop the clock.Empty/full level of the registers can be determined by detecting the pulse signal of the two-phase asynchronous register,and then control the wrapper to sample input/output data.Sender wrapper and receiver wrapper consist of C elements and threshold gates,which ensure the quasi delay-insensitive characteristics and enhance the robustness.Simulations under different technology corners are implemented based on SMIC 0.18μm standard CMOS. Sender wrapper and receiver wrapper allow synchronous modules to work at the speed of 3.08 GHz and 2.98 GHz respectively with average dynamic power consumption of 1.727 mW and 1.779 mW.Its advantages of high-throughput,low-power, scalability and robustness make it a viable option for high-speed low-power interconnection of network-on-chip.

A low-power high-throughput link splitting router for NoCs

In this paper, we propose a technique for lowering the latency of the communication in a NoC （network on chip）. The technique, which can support two qualities of service （QoS）, i.e., the guaranteed throughput （GT） and best effort （BE）, is based on splitting a wider link into narrower links to increase throughput and decrease latency in the NoC. In addition, to ease the synchronization and reduce the crosstalk, we use the l-of-4 encoding for the smaller buses. The use of the encoding in the proposed NoC architecture considerably lowers the latency for both BE and GT packets. In addition, the bandwidth is increased while the power consumption of the links is reduced.