This paper investigates the untraditional approach of contention resolution in Wavelength Division Multiplexing (WDM) Optical Packet Switching (OPS). The most striking characteristics of the developed switch architect...This paper investigates the untraditional approach of contention resolution in Wavelength Division Multiplexing (WDM) Optical Packet Switching (OPS). The most striking characteristics of the developed switch architecture are: (1) Contention resolution is achieved by a combined sharing of Fiber Delay-Lines (FDLs) and Tunable Optical Wavelength Converters (TOWCs); (2) FDLs are arranged in non-degenerate form, i.e., non-uniform distribution of the delay lines; (3) TOWCs just can perform wavelength conversion in partial continuous wavelength channels, i.e., sparse wavelength conversion. The concrete configurations of FDLs and TOWCs are described and analyzed under non-bursty and bursty traffic scenarios. Simulation results demonstrate that for a prefixed packet loss probability constraint, e.g., 10-6, the developed architecture provides a different point of view in OPS design. That is, combined sharing of FDLs and TOWCs can, effectively, obtain a good tradeoff between the switch size and the cost, and TOWCs which are achieved in sparse form can also decrease the implementing complexity.展开更多
An innovative solution to design phase and quadrature pulsed coupled oscillators systems through electromagnetic waveguides is described in this paper. Each oscillator is constituted by an LC differential resonator re...An innovative solution to design phase and quadrature pulsed coupled oscillators systems through electromagnetic waveguides is described in this paper. Each oscillator is constituted by an LC differential resonator refilled through a couple of current pulse generator circuits. The phase and quadrature coupling between the two differential oscillators is achieved using delayed replicas of generated fundamentals from a resonator as driving signal of pulse generator injecting in the other resonator. The delayed replicas are obtained by microstrip-based delay-lines. A 2.4 - 2.5 GHz VCO has been implemented in a 150 nm RF CMOS process. Simulations showed at 1 MHz offset a phase noise of -139.9 dBc/Hz and a FOM of -189.1 dB.展开更多
A major concern in modern smart-phones and hand-held devices is a way of mitigating the time interval error (TIE) perceived at high-speed digital transits along the traces of the circuit-board (rigid and or flexible) ...A major concern in modern smart-phones and hand-held devices is a way of mitigating the time interval error (TIE) perceived at high-speed digital transits along the traces of the circuit-board (rigid and or flexible) used in baseband infrastructures. Indicated here is a way of adopting a planar fractal inductor configuration to improvise the necessary time-delay in the transits of digital signal phase jitter and reduce the TIE. This paper addresses systematic design considerations on fractal inductor geometry commensurate with practical aspects of its implementation as delaylines in the high-speed digital transports at the baseband operations of smart-phone infrastructures. Experimental results obtained from a test module are presented to illustrate the efficacy of the design and acceptable delay performance of the test structure commensurate with the digital transports of interest.展开更多
The design principle for a multi-wire proportional chamber with a cathode strip and delay-line readout is described. A prototype chamber of a size of 10 cm×10 cm was made together with the readout electronics cir...The design principle for a multi-wire proportional chamber with a cathode strip and delay-line readout is described. A prototype chamber of a size of 10 cm×10 cm was made together with the readout electronics circuit. A very clean signal with very low background noise was obtained by applying a transformer between the delay-line and the pre-amplifier in order to match the resistance. Along the anode wire direction a position resolution of less than 0.5 mm was achieved with a ^55Fe-5.9 keV X ray source. The simple structure, large effective area and high position resolution allow the application of a gas chamber of this kind to many purposes.展开更多
By using an optical system simulator, we investigated the tunable delay-line with an optical SSB modulator and an optical fiber loop, where the delay can be controlled by the electric signal fed to the modulator.
An X-ray imaging device based on a triple-GEM （Gas Electron Multiplier） detector, a fast delay-line circuit with 700 MHz cut-off frequency and two dimensional readout strips with 150 μm width on the top and 250 μm...An X-ray imaging device based on a triple-GEM （Gas Electron Multiplier） detector, a fast delay-line circuit with 700 MHz cut-off frequency and two dimensional readout strips with 150 μm width on the top and 250 μm width on the bottom, is designed and tested. The localization information is derived from the propagation time of the induced signals on the readout strips. This device has a good spatial resolution of 150 μm and works stably at an intensity of 105 Hz/mm2 with 8 keV X-rays.展开更多
The design and implementation of a novel ADC architecture called ring-ADC for digital voltage regulator module controllers are presented. Based on the principle of voltage-controlled oscillators＇ transform from volta...The design and implementation of a novel ADC architecture called ring-ADC for digital voltage regulator module controllers are presented. Based on the principle of voltage-controlled oscillators＇ transform from voltage to frequency,the A/D conversion of ring-ADC achieves good linearity and precise calibration against process variations compared with the delay-line ADC. A differential pulse counting discriminator also helps decrease the power consumption of the ring-ADC. It is fabricated with a Chartered 0.35μm CMOS process, and the measurement results of the integral and differential nonlinearity performance are 0.92LSB and 1.2LSB respectively. The maximum gain error measured in ten sample chips is ± 3.85%. With sampling rate of 500kHz and when the voltage regulator module （VRM） works in steady state, the ring-ADC＇s average power consumption is 2.56mW. The ring-ADC is verified to meet the requirements for digital VRM controller application.展开更多
Three large sized glass resistive plate chambers （RPCs） are built and applied to measure the spatial resolution of the detector. The readout strips are collected to a LC delay-line and the time difference is used to...Three large sized glass resistive plate chambers （RPCs） are built and applied to measure the spatial resolution of the detector. The readout strips are collected to a LC delay-line and the time difference is used to determine the position. Cosmic rays are triggered by a set of two scintillation counters and the coincidently measured positions from the three RPCs are used to deduce the position uncertainty. In average a spatial resolution of 0.90 mm （FWHM） is obtained for a single RPC, with a good uniformity across the detection area. This result suggests that large sized glass RPC operating in the avalanche mode is a promising candidate for the muon tomography detection system.展开更多
基金Supported by the National Natural Science Foundation of China (No.69990540).
文摘This paper investigates the untraditional approach of contention resolution in Wavelength Division Multiplexing (WDM) Optical Packet Switching (OPS). The most striking characteristics of the developed switch architecture are: (1) Contention resolution is achieved by a combined sharing of Fiber Delay-Lines (FDLs) and Tunable Optical Wavelength Converters (TOWCs); (2) FDLs are arranged in non-degenerate form, i.e., non-uniform distribution of the delay lines; (3) TOWCs just can perform wavelength conversion in partial continuous wavelength channels, i.e., sparse wavelength conversion. The concrete configurations of FDLs and TOWCs are described and analyzed under non-bursty and bursty traffic scenarios. Simulation results demonstrate that for a prefixed packet loss probability constraint, e.g., 10-6, the developed architecture provides a different point of view in OPS design. That is, combined sharing of FDLs and TOWCs can, effectively, obtain a good tradeoff between the switch size and the cost, and TOWCs which are achieved in sparse form can also decrease the implementing complexity.
文摘An innovative solution to design phase and quadrature pulsed coupled oscillators systems through electromagnetic waveguides is described in this paper. Each oscillator is constituted by an LC differential resonator refilled through a couple of current pulse generator circuits. The phase and quadrature coupling between the two differential oscillators is achieved using delayed replicas of generated fundamentals from a resonator as driving signal of pulse generator injecting in the other resonator. The delayed replicas are obtained by microstrip-based delay-lines. A 2.4 - 2.5 GHz VCO has been implemented in a 150 nm RF CMOS process. Simulations showed at 1 MHz offset a phase noise of -139.9 dBc/Hz and a FOM of -189.1 dB.
文摘A major concern in modern smart-phones and hand-held devices is a way of mitigating the time interval error (TIE) perceived at high-speed digital transits along the traces of the circuit-board (rigid and or flexible) used in baseband infrastructures. Indicated here is a way of adopting a planar fractal inductor configuration to improvise the necessary time-delay in the transits of digital signal phase jitter and reduce the TIE. This paper addresses systematic design considerations on fractal inductor geometry commensurate with practical aspects of its implementation as delaylines in the high-speed digital transports at the baseband operations of smart-phone infrastructures. Experimental results obtained from a test module are presented to illustrate the efficacy of the design and acceptable delay performance of the test structure commensurate with the digital transports of interest.
基金Major State Basic Research Development Program of China (2007CB815002)NSFC (10775003, 10827505)
文摘The design principle for a multi-wire proportional chamber with a cathode strip and delay-line readout is described. A prototype chamber of a size of 10 cm×10 cm was made together with the readout electronics circuit. A very clean signal with very low background noise was obtained by applying a transformer between the delay-line and the pre-amplifier in order to match the resistance. Along the anode wire direction a position resolution of less than 0.5 mm was achieved with a ^55Fe-5.9 keV X ray source. The simple structure, large effective area and high position resolution allow the application of a gas chamber of this kind to many purposes.
文摘By using an optical system simulator, we investigated the tunable delay-line with an optical SSB modulator and an optical fiber loop, where the delay can be controlled by the electric signal fed to the modulator.
基金Supported by National Natural Science Foundation of China (10575101)
文摘An X-ray imaging device based on a triple-GEM （Gas Electron Multiplier） detector, a fast delay-line circuit with 700 MHz cut-off frequency and two dimensional readout strips with 150 μm width on the top and 250 μm width on the bottom, is designed and tested. The localization information is derived from the propagation time of the induced signals on the readout strips. This device has a good spatial resolution of 150 μm and works stably at an intensity of 105 Hz/mm2 with 8 keV X-rays.
文摘The design and implementation of a novel ADC architecture called ring-ADC for digital voltage regulator module controllers are presented. Based on the principle of voltage-controlled oscillators＇ transform from voltage to frequency,the A/D conversion of ring-ADC achieves good linearity and precise calibration against process variations compared with the delay-line ADC. A differential pulse counting discriminator also helps decrease the power consumption of the ring-ADC. It is fabricated with a Chartered 0.35μm CMOS process, and the measurement results of the integral and differential nonlinearity performance are 0.92LSB and 1.2LSB respectively. The maximum gain error measured in ten sample chips is ± 3.85%. With sampling rate of 500kHz and when the voltage regulator module （VRM） works in steady state, the ring-ADC＇s average power consumption is 2.56mW. The ring-ADC is verified to meet the requirements for digital VRM controller application.
基金Supported by National Natural Science Foundation of China(11035001, 10827505, 10775003)
文摘Three large sized glass resistive plate chambers （RPCs） are built and applied to measure the spatial resolution of the detector. The readout strips are collected to a LC delay-line and the time difference is used to determine the position. Cosmic rays are triggered by a set of two scintillation counters and the coincidently measured positions from the three RPCs are used to deduce the position uncertainty. In average a spatial resolution of 0.90 mm （FWHM） is obtained for a single RPC, with a good uniformity across the detection area. This result suggests that large sized glass RPC operating in the avalanche mode is a promising candidate for the muon tomography detection system.
