Experimental and computational investigation of novel vertical tail buffet suppression method for high sweep delta wing

Our research aim is to investigate the buffet alleviation effect of static or vibrating bulges attached on the forebody surface of the model.Experiments and numerical simulations on a model consisting of a sharp-edged,70°-leading edge sweep delta wing and twin swept back vertical tails were conducted.Models with different bulges were tested and computed at 10 and 20 m/s of free stream velocity at angles of attack ranging from 20°–50°.Dynamic strain gauge and multichannel data acquisition and analysis system were employed for the measurement of unsteady root strain on the vertical tails.Experimental and computational results show that both static and vibrating bulges behave effectively as a novel tool to alleviate tail buffet,and the alleviation effect depends largely on the vibrating frequency.Besides,one-sided bulge can only alleviate the buffeting response for the tail of the same side,and it has no obvious alleviation effect for the opposite tail.Results of the spectral analysis reveal that there are generally three peaks of spectral density for aircrafts of this configuration,and bulges used in this paper could alleviate tail buffeting,but the total lift and drag of the whole model show no obvious deviation compared to the base model and the dominant frequency of the vibration of the tails has not shifted.

A single die 1.2 V 55 to 95 dB DR delta sigma ADC with configurable modulator and OSR

A single die 1.2 V multi-stage noise shaping（Mash） 2-2 delta sigma analog to digital converter（ADC）for wide applications is implemented. The configurable Mash 2-2 modulator with a new decimation filter design is presented to achieve wide and high dynamic range（DR） for multiple practical applications. The novel modulator can be configured as a Mash 2-2 modulator for high precision or a 2-order modulator for low DR. The decimation filter is designed to select the OSR flexibly among cascaded integrator comb（CIC） filter and two half-band filters（HBF）. The serial peripheral interface（SPI） can be used to adjust the sampling frequency and the oversampling ratio（OSR）. The design was fabricated in a 0.13 m CMOS process with an area of 0.91 mm2and a total power of 5.2 mW. The measurement results show that the dynamic range（DR） of the proposed ADC can change from 55to 95 dB with the configurable OSR from 16 to 256. The spurious free dynamic range（SFDR） and signal-to-noise distortion ratio（SNDR） can get 99 dB and 86.5 dB, respectively.