期刊文献+
共找到4篇文章
< 1 >
每页显示 20 50 100
Design and application of a depletion-mode NJFET in a high-voltage BiCMOS process
1
作者 刘勇 唐昭焕 +3 位作者 王志宽 杨永晖 杨卫东 胡永贵 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2010年第8期70-73,共4页
A novel depletion-mode NJFET compatible high-voltage BiCMOS process is proposed and experimentally demonstrated with a four-branch 12-bit DAC(digital-to-analog converter).With this process,an NJFET with a pinch-off ... A novel depletion-mode NJFET compatible high-voltage BiCMOS process is proposed and experimentally demonstrated with a four-branch 12-bit DAC(digital-to-analog converter).With this process,an NJFET with a pinch-off voltage ofabout-1.5 V and a breakdown voltage of about 16 V,an NLDDMOS(N-type lightly-dosed-drain in MOS) with a turn-on voltage of about 1.0 V and a breakdown voltage of about 35 V,and a Zener diode with a reverse voltage of about 5.6 V were obtained.Measurement results showed that the converter had a reference temperature coefficient of less than±25 ppm/℃,a differential coefficient error of less than±0.3 LSB,and a linear error of less than±0.5 LSB.The depletion-mode NJFET and its compatible process can also be widely used for high-voltage ADCs or DACs. 展开更多
关键词 depletion-mode njfet high-voltage BiCMOS process ADC DAC temperature coefficient
原文传递
Lateral depletion-mode 4H-SiC n-channel junction field-effect transistors operational at 400℃
2
作者 刘思成 汤晓燕 +4 位作者 宋庆文 袁昊 张艺蒙 张义门 张玉明 《Chinese Physics B》 SCIE EI CAS CSCD 2021年第2期567-572,共6页
This paper presents the development of lateral depletion-mode n-channel 4 H-SiC junction field-effect transistors(LJFETs)using double-mesa process toward high-temperature integrated circuit(IC)applications.At room tem... This paper presents the development of lateral depletion-mode n-channel 4 H-SiC junction field-effect transistors(LJFETs)using double-mesa process toward high-temperature integrated circuit(IC)applications.At room temperature,the fabricated LJFETs show a drain-to-source saturation current of 23.03μA/μm,which corresponds to a current density of 7678 A/cm^(2).The gate-to-source parasitic resistance of 17.56 kΩ·μm is reduced to contribute only 13.49%of the on-resistance of 130.15 kΩ·μm,which helps to improve the transconductance up to 8.61μS/μm.High temperature characteristics of LJFETs were performed from room temperature to 400℃.At temperatures up to 400℃in air,it is observed that the fabricated LJFETs still show normally-on operating characteristics.The drain-to-source saturation current,transconductance and intrinsic gain at 400℃are 7.47μA/μm,2.35μS/μm and 41.35,respectively.These results show significant improvement over state-of-the-art and make them attractive for high-temperature IC applications. 展开更多
关键词 junction field-effect transistors high temperature 4H-SIC depletion-mode
下载PDF
一种具有辅助耗尽效应的BiCMOS NJFET
3
作者 冯金荣 冯全源 陈晓培 《微电子学》 CAS CSCD 北大核心 2018年第5期682-685,共4页
基于BiCMOS工艺,提出了一种N沟道结型场效应晶体管(NJFET)。该NJFET通过在MOS管的栅极与漏极之间的N阱层上注入P型杂质,形成P型底部埋层(P-BOT)层。利用PBOT层的辅助耗尽效应来避免NJFET过早横向击穿,达到提高NJFET源-漏击穿电压的目的... 基于BiCMOS工艺,提出了一种N沟道结型场效应晶体管(NJFET)。该NJFET通过在MOS管的栅极与漏极之间的N阱层上注入P型杂质,形成P型底部埋层(P-BOT)层。利用PBOT层的辅助耗尽效应来避免NJFET过早横向击穿,达到提高NJFET源-漏击穿电压的目的。采用Sentaurus TCAD软件对该BiCMOS NJFET的击穿电压进行仿真。结果表明,该NJFET的击穿电压达104V,在相同N阱掺杂浓度下,比传统NJFET提高了57.6%。 展开更多
关键词 N沟道结型场效应晶体管 降低表面电场 击穿电压 BICMOS
下载PDF
一种实用的高压BiCMOS关键工艺技术研究 被引量:1
4
作者 唐昭焕 刘勇 +3 位作者 王志宽 谭开洲 杨永晖 胡永贵 《微电子学》 CAS CSCD 北大核心 2010年第5期758-761,共4页
提出了一种实用的高压BiCMOS工艺。该工艺集成了高性能耗尽型NJFET、NPN、VPNP、高压NMOS、高压PMOS、NMOS、PMOS、齐纳二极管,以及铬硅电阻、磷注入电阻等有源和无源器件。NJFET的夹断电压为-1.5 V,击穿电压为17 V;高压MOS管的击穿电压... 提出了一种实用的高压BiCMOS工艺。该工艺集成了高性能耗尽型NJFET、NPN、VPNP、高压NMOS、高压PMOS、NMOS、PMOS、齐纳二极管,以及铬硅电阻、磷注入电阻等有源和无源器件。NJFET的夹断电压为-1.5 V,击穿电压为17 V;高压MOS管的击穿电压为37 V;齐纳二极管在25μA时其反向击穿电压为5.5 V。使用该工艺,研制了一款低压差线性稳压器(LDO),基准源静态电流小于1.5μA。该工艺还可广泛应用于高压A/D、D/A转换器的研制。 展开更多
关键词 线性兼容CMOS工艺 BICMOS工艺 njfet VPNP 低压差线性稳压器
下载PDF
上一页 1 下一页 到第
使用帮助 返回顶部