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基于文件流的.NET串行化技术
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作者 王雪峰 《铜陵学院学报》 2008年第5期72-72,74,共2页
.NET中的串行化能使编程人员获得一个对象的实例,并将它转换为一种易于在网络上传播或者在数据库、文件系统上存储的数据流格式,文章详细介绍了常用的串行化方法和各自优缺点。
关键词 串行化 XML SERIALIZABLE Deserialize
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Design of a New Serializer and Deserializer Architecture for On-Chip SerDes Transceivers
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作者 Nivedita Jaiswal Radheshyam Gamad 《Circuits and Systems》 2015年第3期81-92,共12页
The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of... The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of interconnects and offers remarkable benefits in context with power consumption, area congestion and crosstalk. This paper reports a design of a new Serializer and Deserializer architecture for basic functional operations of serialization and deserialization used in On-Chip SerDes Transceiver. This architecture employs a design technique which samples input on both edges of clock. The main advantage of this technique which is input is sampled with lower clock (half the original rate) and is distributed for the same functional throughput, which results in power savings in the clock distribution network. This proposed Serializer and Deserializer architecture is designed using UMC 180 nm CMOS technology and simulation is done using Cadence Spectre simulator with a supply voltage of 1.8 V. The present design is compared with the earlier published similar works and improvements are obtained in terms of power consumption and area as shown in Tables 1-3 respectively. This design also helps the designer for solving crosstalk issues. 展开更多
关键词 SERDES TRANSCEIVER Serializer DESERIALIZER SoC CADENCE
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