Low overhead design-for-testability for scan-based delay fault testing

An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generation process complex and produce lower coverage for scan-based designs as compared with non-scan designs, whereas techniques such as enhanced-scan test can make the test easy but need an extra holding latch to add substantial hardware overhead. A new tri-state holding logic is presented to replace the common holding latch in enhanced-scan test to get a substantial low hardware overhead. This scheme can achieve low delay overhead by avoiding the holding latch on the critical timing scan path. What＇s more, this method can also keep the state and signal activity in the combinational circuit from the scan during data scan-in operation to reduce the power dissipation. Experiment results on a set of ISCAS89 benchmarks show the efficiency of the proposed scheme.

An Application of Paraconsistent Annotated Logic for Design Software Testing Strategies

Nowadays, application model systems for decision-making based on non-classical logic such as Paraconsistent Logic are used successfully in the treatment of uncertainties. The method presented in this paper is based on the fundamental concepts of Paraconsistent Annotated Logic with annotation of 2 values (PAL2v). In this study, two algorithms based on PAL2v are presented gradually, to extract the effects of the contradiction in signals of information from a database of uncertain knowledge. The Paraconsistent Extractors Algorithms of Contradiction Effect-Para Extrctr is applied to filters of networks of analyses (PANets) of signal information, where uncertain and contradictory signals may be found. Software test case scenarios are subordinated to an application model of Paraconsistent decision-making, which provides an analysis using Paraconsistent Logic in the treatment of uncertainties for design software testing strategies. This quality-quantity criterion to evaluate the software product quality is based on the characteristics of software testability analysis. The Para consistent reasoning application model system presented in this case study, reveals itself to be more efficient than the traditional methods because it has the potential to offer an appropriate treatment to different originally contradicting source information.

Compact-Parity Testing and Testable Design

Parity testing is one of the compact testing techniques, which, traditionally, relies on applying all 2^n input combinations to an n-input combinational circuit without need of knowing the implementation of the circuits under test. The faults can be detected just by observing and comparing its parity of whole output of circuit with the expectation one. The way seemed to be less interesting to the test eagineers in the past days, mainly due to the reasons of its exhaustive testing and time-cousuming, which became a barrier as the number of input lines gets growing. However its great facility and convenience in testing still interest to the engineers who need to have a quick look at the qualities of the circuits without generating the test patterns for a given circuit to be tested. In this paper, a new approach called pseudo-parity testing is presented to deal with the dilemma we are facing： i. e. to change an exhaustive parity testing into a non-exhaustive one, followed by a pseudo- parity testable design to help realize the new way of pseudo-parity testing. The idea of pseudo-parity testing presented in this paper may resume its spirits towards its promising future.

Design for Testability Features of Godson-3 Multicore Microprocessor

This paper describes the design for testability （DFT） challenges and techniques of Godson-3 microprocessor, which is a scalable multicore processor based on the scalable mesh of crossbar （SMOC） on-chip network and targets high-end applications. Advanced techniques are adopted to make the DFT design scalable and achieve low-power and low-cost test with limited IO resources. To achieve a scalable and flexible test access, a highly elaborate test access mechanism （TAM） is implemented to support multiple test instructions and test modes. Taking advantage of multiple identical cores embedding in the processor, scan partition and on-chip comparisons are employed to reduce test power and test time. Test compression technique is also utilized to decrease test time. To further reduce test power, clock controlling logics are designed with ability to turn off clocks of non-testing partitions. In addition, scan collars of CACHEs are designed to perform functional test with low-speed ATE for speed-binning purposes, which poses low complexity and has good correlation results.

Empirical Approach for Planning and Designing Constant Stress Accelerated Life Tests

Accelerated life testing(ALT)has been widely used to obtain information about the product's life characteristics at normal conditions in a relatively short period of time.Two key issues with ALT are test design and data analysis.The test design of constant stress ALT was studied in this paper.The test design usually combines engineering experiences with optimization models.Such approaches are hard to be implemented by practitioners.A"pure"empirical approach was presented to address this issue.With the proposed approach,some of the decision variables are determined based on the results from the literature,some of the other variables are determined based on engineering analysis and /or judgment,and the remaining variables are determined based on the empirical relations developed in this paper.A real-world example is included to illustrate the appropriateness of the proposed approach.

A DFT Method for Single-Control Testability of RTL Data Paths for BIST

This paper presents a new BIST method for RTL data paths based on single-control testability, a new concept of testability. The BIST method adopts hierarchical test. Test pattern generators are placed only on primary inputs and test patterns are propagated to and fed into each module. Test responses are similarly propagated to response analyzers placed only on primary outputs. For the propagation of test patterns and test responses paths existing in the data path are utilized. The DFT method for the single-control testability is also proposed. The advantages of the proposed method are high fault coverage (for single Stuck-at faults), low hardware overhead and capability of at-speed test. Moreover, test patterns generated by test pattern generators can be fed into each module at consecutive system clocks, and thus, the BIST can also detect some faults of other fault models (e.g., transition faults and delay faults) that require consecutive application of test patterns at speed of system clock.

Testable Design and BIST Techniques for Systolic Motion Estimators in Transform Domain

Testable design techniques for systolic motion estimators based on M-testability conditions are proposed in this paper. The whole motion estimator can be viewed as a two-dimensional iterative logic array （ILA） of processing elements （PEs） and multiplying elements （MULs）. The functions of each PE and MUL are modified to be bijective to meet the M-testable conditions. The number of test patterns is 2^w, where w denotes the word length of a PE. The proposed testable design techniques are also suitable for built-in self-test implementation. According to experimental results, our approaches can achieve 99.27 % fault coverage. The area overhead is about 9 %. To verify our approaches, an experimental chip is also implemented.

Quantifying Reusability of Object Oriented Design: A Testability Perspective

The quality factor of class diagram is critical because it has a significant influence on overall quality of the product, delivered finally. Testability analysis, when done early in the software creation process, is a criterion of critical importance to software quality. Reusability is an important quality factor to testability. Its early measurement in object oriented software especially at design phase, allows a design to be reapplied to a new problem without much extra effort. This research paper proposes a research framework for quantification process and does an extensive review on reusability of object oriented software. A metrics based model “Reusability Quantification of Object Oriented Design” has been proposed by establishing the relationship among design properties and reusability and justifying the correlation with the help of statistical measures. Also, “Reusability Quantification Model” is empirically validated and contextual significance of the study shows the high correlation for model acceptance. This research paper facilitates to software developers and designer, the inclusion of reusability quantification model to access and quantify software reusability for quality product.

复杂系统测试性设计与故障诊断策略研究进展

测试性设计是提高系统可靠性、安全性、维修性、保障性的重要前沿技术,决定了系统故障检测率和隔离率,直接影响系统的维护(测试)成本。系统测试性设计包含结构化设计、模型化设计、数据驱动设计等多种设计策略。其中,数据驱动设计于近年逐渐兴起并成为重要发展方向之一,该类方法通过对系统测试与故障之间的关系进行建模,依据测试结果进行故障推理,形成故障诊断方案。首先,简要回顾了系统测试性设计的发展历程;其次,重点介绍了测试性设计的研究进展,分析总结了结构化、模型化、数据驱动3类测试方案;然后,介绍了测试性诊断策略构建,根据测试方案中的建模方法确定诊断策略的构建技术,并总结归纳了每类技术的研究特点和适用性;最后,探讨了当前复杂系统测试性设计面临的挑战性问题和可能的未来研究方向。

高放废物处置地下实验室现场试验数据管理顶层设计

我国高放废物地质处置研发已经进入地下实验室建设的关键阶段。在地下实验室建设和运行期间,将开展大量现场试验,这些试验数据具有传输距离长、采集周期长、数据类型多和数据量大等特点,同时数据质量、安全与可追溯性要求高,数据管理难度较大。通过分析我国高放废物地质处置北山地下实验室现场试验数据特点,以iS3智慧数据服务系统为基础,提出现场试验数据管理顶层设计方法,为现场试验和科研工作顺利开展提供重要的数据管理支撑。

Adding Pseudo-Random Test Sequence Generator in the Test Simulator for DFT Approach

This paper presents modified version of a realistic test tool suitable to Design For Testability （DFT） and Built-ln Self Test （BIST） environments. A comprehensive tool is developed in the form of a test simulator. The simulator is capable of providing a required goal of test for the Circuit Under Test （CUT）. The simulator uses the approach of fault diagnostics with fault grading procedures to provide the optimum tests. The current version of the simulator embeds features of exhaustive and pseudo-random test generation schemes along with the search solutions of cost effective test goals. The simulator provides facilities of realizing all possible pseudo-random sequence generators with all possible combinations of seeds. The tool is developed on a common Personal Computer （PC） platform and hence no special software is required. Thereby, it is a low cost tool hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any CUT. The developed tool incorporates flexible Graphical User Interface （GUI） procedures and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational purposes for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safe-reliable-testable digital logic designs.

Ethernet Controller SoC Design and Its Low-Power DFT Considerations

In this paper, an Ethernet controller SoC solution and its low power design for testability （DFT） for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit （MCU）, media access control （MAC） circuit and embedded memories such as static random access memory （SRAM）, read only memory （ROM） and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits： the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is employed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test （BIST）. By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by using 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor （CMOS） technology, the die area is 4.8×4.6 mm^2. Test results show that the maximum throughput of Ethemet packets may reach 7Mb·s^1.

芯粒互连测试向量生成与测试方法研究

基于芯粒的2.5D和3D集成系统产品都具有大量的芯粒间互连,不可避免地会出现各种制造缺陷,互连测试对于提高2.5D和3D集成系统产品规模生产过程中的质量和产量至关重要。在研究传统的I-ATPG和真/补测试算法等互连测试方法的基础上提出了一种新的代码字编码方法,只需要4个代码字即可对所有矩形网络和六角网络进行代码字编码。设计了一种基于IEEE1838标准的芯粒集成系统测试架构,给出了一种典型的双芯粒互连电路并进行了测试和仿真验证,以系统性地介绍芯粒间互连测试技术。

Area-time associated test cost model for SoC and lower bound of test time

A novel test access mechanism （TAM） architecture with multi test-channel （TC） based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip （SoC） test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC02 test benchmark.

Research of Board-Level BIT Technology Based on Boundary-Scan Architecture

The boundary scan architecture and its basic principle of board level built in test(BIT) technology are presented. A design for board level built in test and the method to implement test tool are brought forward.

SoC芯片扫描链测试设计与实现

阐述针对SoC芯片,进行压缩测试、stuck-at测试和全速测试的设计,并通过Tessent软件插入扫描链和生成ATPG自动测试向量。结果表明,芯片固定型故障、时延相关故障的覆盖率满足测试要求。

基于鸿劲分选机的通用SLT实装板设计方法研究

主要基于鸿劲系列分选机的测试插座要求、硬件接口要求和软件通讯协议设计了一种既可以手测又可以放在分选机上实现自动化测试的通用实装板。不同于常见的实装自动化测试插座,基于鸿劲系列分选机的自动化测试插座为防止芯片叠料和放歪会在插座座体上面开光纤传感器的孔,硬件接口一般要求是固定的测试接口,要根据分选机的接口要求去设计实装板,分选机的软件通讯协议也要按照分选机本身的协议框架去编写测试程序,根据以上3点结合实际项目经验总结出一套通用实装板的设计方法,可有效地提高实装板软硬件设计效率。

城际动车组空调系统设计

空调系统的正常运行是保障列车内舒适环境的关键。针对城际动车组的空调系统设计,文章介绍了空调系统的顶层技术指标、设计要点及相关计算,从客室空调系统及其通风与控制系统、司机室空调系统等方面阐述了空调系统的整体布局,并对车内压力波控制、智能运维及健康管理、试验验证方法等进行了分析说明。

A novel approach of testability modeling and analysis for PHM systems based on failure evolution mechanism

Prognostics and health management （PHM） significantly improves system availability and reliability, and reduces the cost of system operations. Design for testability （DFT） developed concurrently with system design is an important way to improve PHM capability. Testability modeling and analysis are the foundation of DFT. This paper proposes a novel approach of testability modeling and analysis based on failure evolution mechanisms. At the component level, the fault progression-related information of each unit under test （UUT） in a system is obtained by means of failure modes, evolution mechanisms, effects and criticality analysis （FMEMECA）, and then the failure-symptom dependency can be generated. At the system level, the dynamic attributes of UUTs are assigned by using the bond graph methodology, and then the symptom-test dependency can be obtained by means of the functional flow method. Based on the failure-symptom and symptom-test dependencies, testability analysis for PHM systems can be realized. A shunt motor is used to verify the application of the approach proposed in this paper. Experimental results show that this approach is able to be applied to testability modeling and analysis for PHM systems very well, and the analysis results can provide a guide for engineers to design for testability in order to improve PHM performance.

基于三维线性反馈移位寄存器的三维堆叠集成电路可重构测试方案

三维堆叠集成电路(3D SIC)结构复杂,相较于二维集成电路(2D IC),设计有效的测试结构以降低测试成本更加困难。为降低3D SIC的测试成本,提出一种基于线性反馈移位寄存器(LFSR)的能够有效适应3D SIC不同测试阶段的三维LFSR(3D-LFSR)测试结构。3D-LFSR结构能够在堆叠前独立进行测试;在堆叠后,复用堆叠前的测试结构,并重构为一个适合当前待测电路的测试结构,且重构后的测试结构能进一步降低测试成本。基于3D-LFSR结构,设计了测试数据处理方法和测试流程,并采用混合测试模式以降低测试时间。实验结果表明,相较于双LFSR结构,3D-LFSR结构的平均功耗降低了40.19%,平均面积开销降低了21.31%,测试数据压缩率提升了5.22个百分点;相较于串行测试模式,采用混合测试模式的平均测试时间减少了20.49%。