Efficient multiuser detector based on box-constrained deregularization and its FPGA design

Multiuser detection can be described as a quadratic optimization problem with binary constraint. Many techniques are available to find approximate solution to this problem. These tech- niques can be characterized in terms of complexity and detection performance. The ＂efficient frontier＂ of known techniques include the decision-feedback, branch-and-bound and probabilistic data association detectors. The presented iterative multiuser detection technique is based on joint deregularized and box-constrained so- lution to quadratic optimization with iterations similar to that used in the nonstationary Tikhonov iterated algorithm. The deregulari- zation maximizes the energy of the solution, this is opposite to the Tikhonov regularization where the energy is minimized. However, combined with box-constraints, the deregularization forces the solution to be close to the binary set. We further exploit the box- constrained dichotomous coordinate descent （DCD） algorithm and adapt it to the nonstationary iterative Tikhonov regularization to present an efficient detector. As a result, the worst-case and aver- age complexity are reduced down to K28 and K2~ floating point operation per second, respectively. The development improves the ＂efficient frontier＂ in multiuser detection, which is illustrated by simulation results. Finally, a field programmable gate array （FPGA） design of the detector is presented. The detection performance obtained from the fixed-point FPGA implementation shows a good match to the floating-point implementation.

A parallel complex divider architecture based on DCD iterations for computing complex division in MVDR beamformer

This paper presents a hardware architecture using mixed pipeline and parallel processing for complex division based on dichotomous coordinate descent(DCD) iterations. The objective of the proposed work is to achieve low-latency and resource optimized complex divider architecture in adaptive weight computation stage of minimum variance distortionless response(MVDR)algorithm. In this work, computation of complex division is modeled as a 2×2 linear equation solution problem and the DCD algorithm allows linear systems of equations to be solved with high degree of computational efficiency. The operations in the existing DCD algorithm are suitably parallel pipelined and the performance is optimized to 2 clock cycles per iteration. To improve the degree of parallelism, a parallel column vector read architecture is devised.The proposed work is implemented on the field programmable gate array(FPGA) platform and the results are compared with state-of-art literature. It concludes that the proposed architecture is suitable for complex division in adaptive weight computation stage of MVDR beamformer. We demonstrate the performance of the proposed architecture for MVDR beamformer employed in medical ultrasound imaging applications.