With a 45 nm process technique, the shrinking silicon feature size brings in a high-k/metal gate which significantly exacerbates the positive bias temperature instability （PBTI） and time-dependent dielectric breakdo...With a 45 nm process technique, the shrinking silicon feature size brings in a high-k/metal gate which significantly exacerbates the positive bias temperature instability （PBTI） and time-dependent dielectric breakdown （TDDB） effects of a NMOS transistor. However, previous works presented delay models to characterize the PBTI or TDDB individually. This paper demonstrates that the delay caused by the joint effects of PBTI and TDDB widely differs from the cumulated result of the delay caused by the PBT｜ and TDDB, respectively, with the experiments on an inverter chain. This paper proposes a hybrid aging delay model comprising both the PBTI and TDDB effects by analyzing the relationship between the aging propagation delay and the inherent delay of the gate. Experimental results on the logic gates under 45 nm, 32 nm, 22 nm, and 16 nm CMOS technologies show that the maximum error between the proposed model and the actual value is less than 2.5%, meanwhile the average error is about 1.5%.展开更多
A method was developed to estimate EEPROM device life based on the consistency for break- down charge, QBD, for constant voltage time dependent dielectric breakdown （TDDB） and constant current TDDB stress tests. Alt...A method was developed to estimate EEPROM device life based on the consistency for break- down charge, QBD, for constant voltage time dependent dielectric breakdown （TDDB） and constant current TDDB stress tests. Although an EEPROM works with a constant voltage, QBD for the tunnel oxide can be extracted using a constant current TDDB. Once the charge through the tunnel oxide, △QFG, is measured, the lower limit of the EEPROM life can be related to QBD/△QFG. The method is reached by erase/write cycle tests on an EEPROM.展开更多
基金supported by the National Natural Science Foundation of China under Grant No.61371025 and No.61274036
文摘With a 45 nm process technique, the shrinking silicon feature size brings in a high-k/metal gate which significantly exacerbates the positive bias temperature instability （PBTI） and time-dependent dielectric breakdown （TDDB） effects of a NMOS transistor. However, previous works presented delay models to characterize the PBTI or TDDB individually. This paper demonstrates that the delay caused by the joint effects of PBTI and TDDB widely differs from the cumulated result of the delay caused by the PBT｜ and TDDB, respectively, with the experiments on an inverter chain. This paper proposes a hybrid aging delay model comprising both the PBTI and TDDB effects by analyzing the relationship between the aging propagation delay and the inherent delay of the gate. Experimental results on the logic gates under 45 nm, 32 nm, 22 nm, and 16 nm CMOS technologies show that the maximum error between the proposed model and the actual value is less than 2.5%, meanwhile the average error is about 1.5%.
基金Supported the State Important Sci-Tech Special Projects(2009ZX02306-04)
文摘A method was developed to estimate EEPROM device life based on the consistency for break- down charge, QBD, for constant voltage time dependent dielectric breakdown （TDDB） and constant current TDDB stress tests. Although an EEPROM works with a constant voltage, QBD for the tunnel oxide can be extracted using a constant current TDDB. Once the charge through the tunnel oxide, △QFG, is measured, the lower limit of the EEPROM life can be related to QBD/△QFG. The method is reached by erase/write cycle tests on an EEPROM.
