Cache Memory Design for Single Bit Architecture with Different Sense Amplifiers

Most modern microprocessors have one or two levels of on-chip caches to make things run faster,but this is not always the case.Most of the time,these caches are made of static random access memory cells.They take up a lot of space on the chip and use a lot of electricity.A lot of the time,low power is more important than several aspects.This is true for phones and tablets.Cache memory design for single bit architecture consists of six transistors static random access memory cell,a circuit of write driver,and sense amplifiers(such as voltage differential sense amplifier,current differential sense amplifier,charge transfer differential sense amplifier,voltage latch sense amplifier,and current latch sense amplifier,all of which are compared on different resistance values in terms of a number of transistors,delay in sensing and consumption of power.The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34μW of power which shows that power is reduced up to 83%,77.75%reduction in the case of the current differential sense amplifier,39.62%in case of charge transfer differential sense amplifier and 50%in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture.Furthermore,power reduction techniques are applied over different blocks of cache memory architecture to optimize energy.The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078μW of power,i.e.,reduce 28%more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.

Fast-transient techniques for high-frequency DC–DC converters

A 30 MHz voltage-mode controlled buck converter with fast transient responses is presented.An improved differential difference amplifier(DDA)-based Type-III compensator is proposed to reduce the settling times of the converter during load transients,and to achieve near-optimal transient responses with simple PWM control only.Moreover,a hybrid scheme using a digital linear regulator with automatic transient detection and seamless loop transition is proposed to further improve the transient responses.By monitoring the output voltage of the compensator instead of the output voltage of the converter,the proposed hybrid scheme can reduce undershoot and overshoot effectively with good noise immunity and without interrupting the PWM loop.The converter was fabricated in a 0.13μm standard CMOS process using 3.3 V devices.With an input voltage of 3.3 V,the measured peak efficiencies at the output voltages of 2.4,1.8,and 1.2 V are 90.7%,88%,and 83.6%,respectively.With a load step of 1.25 A and rise and fall times of 2 ns,the measured 1%settling times were 220 and 230 ns,with undershoot and overshoot with PWM control of 72 and 76 mV,respectively.They were further reduced to 36 and 38 mV by using the proposed hybrid scheme,and 1%settling times were also reduced to 125 ns.

Synthesis for Current-Mode Sallen-Key Filter Using VDTAs

In this work, an original Sallen-Key second-order low-pass filter is first turned into a current-mode one by means of the adjoint network theorem. Two nodal admittance matrices(NAM) of the filter are then educed. Furthermore, these two matrices are expanded through NAM expansion approach, generating one current-mode Sallen-Key filter, which uses two compact voltage differential trans-conductance amplifiers(VDTAs) and two grounded capacitors, implements not only one low-pass transfer function but two band-pass transfer functions, and provides the non-interrelated control between the natural frequency and quality factor. As an example of the synthesized filter, a second-order VDTA filter with fo=1 MHz, Q=1, HLP=-HBP1=HBP2=1 is designed. The used synthesis approach has been confirmed with the help of circuit and computer analysis.