Toward real-time digital pulse process algorithms for CsI(Tl)detector array at external target facility in HIRFL-CSR

A fully digital data acquisition system based on a field-programmable gate array(FPGA) was developed for a CsI(Tl) array at the external target facility(ETF) in the Heavy Ion Research Facility in Lanzhou(HIRFL). To process the CsI(Tl) signals generated by γ-rays and light-charged ions, a scheme for digital pulse processing algorithms is proposed. Every step in the algorithms was benchmarked using standard γ and α sources. The scheme, which included a moving average filter, baseline restoration, leading-edge discrimination, moving window deconvolution, and digital charge comparison, was subsequently implemented on the FPGA. A good energy resolution of 5.7% for 1.33-MeV γ-rays and excellent α-γ identification using the digital charge comparison method were achieved, which satisfies CsI(Tl) array performance requirements.

Pulse interleaving scheduling algorithm for digital array radar

An online pulse interleaving scheduling algorithm is proposed for a solution to the task scheduling problem in the digital array radar(DAR). The full DAR task structure is explicitly considered in a way that the waiting duration is able to be utilized to transmit or receive subtasks, namely the pulse interleaving,as well as the receiving durations of different tasks are able to be overlapped. The algorithm decomposes the pulse interleaving scheduling analysis into the time constraint check and the energy constraint check, and schedules online all kinds of tasks that are able to be interleaved. Thereby the waiting duration and the receiving duration in the DAR task are both fully utilized. The simulation results verify the performance improvement and the high efficiency of the proposed algorithm compared with the existing ones.

A New Design Method for Variable Digital Filter Based on Field Programmable Gate Array(FPGA)

In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.

A Status Graph Based Control Allocation Algorithm of Digital Micro-Thruster Array for Micro/Nano-Satellites Orbit Control Application

Digital micro-thruster arrays can be used for special missions of micro/nano-satellites with the requirements of high precision and small impulse.This paper presents a novel control allocation algorithm for the digital micro-thruster array,namely status graph based control allocation(SGBCA)algorithm,which aims at finding the optimal micro thrusters combination scheme to realize the sequential control synthesis for micro/nano-satellite during real-time orbit control tasks.A mathematical model is set up for the control allocation of this multivariate over-actuated system.Through dividing thrusters into disjoint segments by offline calculation and combining segments dynamically online to provide a sequence of the required impulse for the micro/nano-satellite,the time complexity of the control allocation algorithm decreases significantly.All levels of impulse can be generated by the digital micro thruster arrays and the service life of the arrays can be extended using the segment converting strategy proposed in this paper.The simulation indicates that the algorithm can satisfy the requirements of real-time orbit control for micro/nano-satellites.

CALL FOR PAPERS Special Issue on Advances in Digital Array Radar(DAR)

Digital array radar(DAR)is the research and development focus all over the world,since it is much more powerful than conventional phased array radar.For example,the Air and Missile Defense Radar(AMDR),also known as the SPY-6,is a next-generation integrated radar including an active electrically scanned array(AESA)that is slated to be 30 times more powerful than the current SPY-1 phased array radar.In China,the Type 346 radar,a multi-function and dual-band naval active phased array radar(APAR),is also highly digitized.It has been proved that conventional radar systems can benefit greatly from digitalization.The performances,such as interference rejection,low sidelobe,target localization and tracking,have been made rapid progress.

Dwell Scheduling Algorithm for Digital Array Radar

Aiming at the problem of resource allocation for digital array radar（ DAR）,a dwell scheduling algorithm is proposed in this paper. Firstly,the integrated priority of different radar tasks is designed,which ensures that the imaging tasks are scheduled without affecting the search and tracking tasks; Then,the optimal scheduling model of radar resource is established according to the constraints of pulse interleaving; Finally,a heuristic algorithm is used to solve the problem and a sparse-aperture cognitive ISAR imaging method is used to achieve partial precision tracking target imaging. Simulation results demonstrate that the proposed algorithm can both improve the performance of the radar system,and generate satisfactory imaging results.

Development of digital organ-on-a-chip to assess hepatotoxicity and extracellular vesicle-based anti-liver cancer immunotherapy

Organ-on-a-chip systems have been increasingly recognized as attractive platforms to assess toxicity and to develop new therapeutic agents.However,current organ-on-a-chip platforms are limited by a“single pot”design,which inevitably requires holistic analysis and limits parallel processing.Here,we developed a digital organ-on-a-chip by combining a microwell array with cellular microspheres,which significantly increased the parallelism over traditional organ-on-a-chip for drug development.Up to 127 uniform liver cancer microspheres in this digital organ-on-a-chip format served as individual analytical units,allowing for analysis with high consistency and quick response.Our platform displayed evident anti-cancer efficacy at a concentration of 10μM for sorafenib,and had greater alignment than the“single pot”organ-on-a-chip with a previous in vivo study.In addition,this digital organ-on-a-chip demonstrated the treatment efficacy of natural killer cell-derived extracellular vesicles for liver cancer at 50μg/mL.The successful development of this digital organ-on-a-chip platform provides high-parallelism and a low-variability analytical tool for toxicity assessment and the exploration of new anticancer modalities,thereby accelerating the joint endeavor to combat cancer.

Research and realization of PWM drive control digitalization for the full digital welding power supply

Pulse width modulation （ PWM） drive control digitalization is the key for the full digital invert power supply. New ideas are proposed, which are based on field programmable gate array （ FPGA ）. First, digital PWM principles are discussed. The primary and secondary current characteristics are analyzed when the transformer is in both normal and magnetic bias conditions. Second, two digitalization methods are put forward after the research on PWM adjustment principles, which are based on the primary current feedback. Though the two methods could restrain magnetic bias, their realization is difficult. A new method is researched on double close-loops to overcome the above shortcomings, which uses the secondary current as the feedback signal and the primary current as the protection signal. Finally, the secondary current control made is discussed and realized. Welding experimental results show that the method has strong flexibility and adaptability, which can be used to realize the full digital welding power supply.

Optimized Implementation for Wave Digital Filter Based Circuit Emulation on FPGA

A binary tree representation is designed in this paper for optimization of wave digital filter（WDF）implementation.To achieve this,an equivalent WDF model of the original circuit is converted into abinary tree representation at first.This WDF binary tree can then be transformed to several topologies with the same implication,since the WDF adaptors have a symmetrical behavior on their ports.Because the WDF implementation is related to field programmable gate array（FPGA）resource usage and the cycle time of emulation,choosing aproper binary tree topology for WDF implementation can help balance the complexity and performance quality of an emulation system.Both WDF-FPGA emulation and HSpice simulation on the same circuit are tested.There is no significant difference between these two simulations.However,in terms of time consumption,the WDF-FPGA emulation has an advantage over the other.Our experiment also demonstrates that the optimized WDF-FPGA emulation has an acceptable accuracy and feasibility.

Beamforming of Whole Airspace Phased Array TT&C System Based on Linear Subarrays

The whole airspace phased array telemetry,track and command(TT&C)system is regarded as the development tendency of next generation TT&C system,and the distribution of the antenna units and the beamforming technology have sparked wide interest in this field.A method for antenna distribution is proposed based on the linear subarrays technology.A symmetrical truncated cone conformal array is composed of the linear subarrays placed on the generatrix.The impact of truncated cone bottom radius and elevation angle on beamforming are studied and simulated.Simulation results verify the system design.

A Planar 4-Bit Reconfigurable Antenna Array Based on the Design Philosophy of Information Metasurfaces

Inspired by the design philosophy of information metasurfaces based on the digital coding concept,a planar 4-bit reconfigurable antenna array with low profile of 0.15λ0(whereλ0is the free-space wavelength)is presented.The array is based on a digital coding radiation element consisting of a 1-bit magnetoelectric(ME)dipole and a miniaturized reflection-type phase shifter(RTPS).The proposed 1-bit ME dipole can provide two digital states of"0"and"1"(with 0°and 180°phase responses)over a wide frequency band by individually exciting its two symmetrical feeding ports.The designed RTPS is able to realize a relative phase shift of 173°.By digitally quantizing its phase in the range of 157.5°,additional eight digital states at intervals of 22.5°are obtained.To achieve low sidelobe levels,a 1:16 power divider based on the Taylor line source method is employed to feed the array,A prototype of the proposed 4-bit antenna array has been fabricated and tested,and the experimental results are in good agreement with the simulations.Scanning beams within a±45°range were measured with a maximum realized gain of 13.4 dBi at12 GHz.The sidelobe and cross-polarization levels are below-14.3 and-23.0 dB,respectively.Furthermore,the beam pointing error is within 0.8°,and the 3 dB gain bandwidth of the broadside beam is 25%.Due to its outstanding performance,the array holds potential for significant applications in radar and wireless communication systems.

Hybrid Authentication Cybersystem Based on Discrete Logarithm, Factorization and Array Entanglements

A hybrid cryptographic system providing digital authentication is described and analyzed in this paper. The proposed cryptosystem incorporates three features: complexity of the discrete logarithm problem, complexity of integer factorization of a product of two large primes and a combination of symmetric and asymmetric keys. In order to make the cryptosystem less vulnerable to cryptanalytic attacks a concept of digital entanglements is introduced. As a result, the proposed cryptographic system has four layers (entanglement-encryption- decryption-disentanglement). It is shown that in certain instances the proposed communication cryptocol is many times faster than the RSA cryptosystem. Examples provided in the paper illustrate details of the proposed authentication cryptocol.

Edge Pattern Based Demosaicking Algorithm of Color Filter Array

An efficient adaptive approximation demosaicking algorithm based on the sampled edge pattern was presented for mosaic images from Bayer color filter array. The proposed algorithm determined edge patterns by four nearest green values surrounding the green interpolation location. Then according to the edge patterns, different adaptive interpolation steps were applied. Simulations on 12 Kodak photos and 15 IMAX high-quality images showed that the proposed method outperformed the other four demosaicking methods (bilinear, effective color interpolation, Lu's method and Chen's method) for average color peak signal to noise ratios and maintained a relatively low complexity owing to constant color-difference interpolation step and a reasonable terminating condition of iteration.

Time Modulated Array Antennas: A Review

Time-modulated array(TMA)antennas,introduce the dimension of time into antenna design to control the radiation patterns and frequency spectral characteristics,thus improve the reconfigurability of array antennas and provide multiple functional-ities.They have great application potential in military and civilian fields,such as precision guidance and mobile communication,and are currently a hot spot of academic research.This article provides a review on the fundamentals and applications of TMAs.First,the basic theory and mathematical formulations of TMAs are introduced.Second,the most important applications of TMAs,namely time-modulated phased arrays(TMPA),are discussed from the perspectives of harmonic suppression and harmonic utiliza-tion,which are used for single-beam and multibeam radiation.Then,we survey the combination of TMA with various types of novel antenna arrays,such as single-channel digital beamforming(DBF)arrays,frequency diverse arrays(FDAs),and retrodirective arrays,to create new hardware implementation methods and enhance their performance.Next,recent advances in dedicated integrated chips for TMA,which have played a significant role in driving the progress of TMAs from academic research to practical applications,are presented.Finally,the challenges and prospects for TMAs are discussed,including new research directions and emerging applica-tion scenarios.

基于DSP与FPGA的变流器通用控制平台研究

提出一种基于DSP和现场可编程门阵列(FPGA)双CPU结构的新型变流器控制系统方案,其中DSP完成变流器控制策略的实现,主要包括:最大功率点跟踪、电压电流双闭环控制、低电压穿越控制、通信功能;FPGA完成三相锁相环控制、AD芯片采样控制、SVPWM波形控制、逻辑输出控制以及各类故障信号检测与停机保护功能,并采用了基于WIFI模块的风电故障信息传输系统。以双馈风电变流器为模型,设计了双馈风力发电变流器系统,完成了两电平与三电平SVPWM控制算法的FPGA实现。最后在自主研发的1.5 MW,2 MW双馈式变流器样机与光伏逆变器样机上进行了大量实验和长期的现场试运行,验证了控制系统平台的可行性与实用性。

10 Gbit/s PRBS tester implemented in FPGA

The design of an FPGA（ field programmable gate array） based programmable SONET （synchronous optical network） OC-192 10 Gbit/s PRBS （pseudo-random binary sequence） generator and a bit interleaved polarity 8 （BIP-8） error detector is presented. Implemented in a parallel feedback configuration, this tester features PRBS generation of sequences with bit lengths of 2^7 - 1,2^10- 1,2^15 - 1,2^23 - land 2^31 - 1 for up to 10 Gbit/s applications with a 10 Gbit/s optical transceiver, via the SFI-4 （OC-192 serdes-framer interface）. In the OC-192 frame alignment circuit, a dichotomy search algorithm logic which performs the functions of word alignment and STM-64/OC192 de-frame speeds up the frame sync logic and reduces circuit complexity greatly. The system can be used as a low cost tester to evaluate the performance of OC-192 devices and components, taking the replacement of precious commercial PRBS testers.

基于机器视觉的坯布疵点实时自动检测平台

为了克服人工检测坯布疵点过程中存在的低效率、高误检率、高漏检率等问题,设计并实现了一款能兼顾实时性和准确性要求的坯布自动检测平台.该平台包括织物传动系统、光源和成像系统、图像采集与处理系统、人机交互系统4个组成部分.在详细阐述了图像采集与处理系统的设计之后,结合AR谱算法对坯布自动检测平台进行了相关调试和试验验证,结果表明该平台已实现了预期的研发要求.

New scale factor correction scheme for CORDIC algorithm

To overcome the drawbacks such as irregular circuit construction and low system throughput that exist in conventional methods, a new factor correction scheme for coordinate rotation digital computer（ CORDIC） algorithm is proposed. Based on the relationship between the iteration formulae, a new iteration formula is introduced, which leads the correction operation to be several simple shifting and adding operations. As one key part, the effects caused by rounding error are analyzed mathematically and it is concluded that the effects can be degraded by an appropriate selection of coefficients in the iteration formula. The model is then set up in Matlab and coded in Verilog HDL language. The proposed algorithm is also synthesized and verified in field-programmable gate array （FPGA）. The results show that this new scheme requires only one additional clock cycle and there is no change in the elementary iteration for the same precision compared with the conventional algorithm. In addition, the circuit realization is regular and the change in system throughput is very minimal.

Design of Parallel Electrical Resistance Tomography System for Measuring Multiphase Flow

ERT(electrical resistance tomography) is effective method for visualization of multiphase flows,offering some advantages of rapid response and low cost,so as to explore the transient hydrodynamics.Aiming at this target,a fully programmable and reconfigurable FPGA(field programmable gate array)-based Compact PCI(peripheral component interconnect) bus linked sixteen-channel ERT system has been presented.The data acquisition system is carefully designed with function modules of signal generator module;Compact PCI transmission module and data processing module(including data sampling,filtering and demodulating).The processing module incorporates a powerful FPGA with Compact PCI bus for communication,and the measurement process management is conducted in FPGA.Image reconstruction algorithms with different speed and accuracy are also coded for this system.The system has been demonstrated in real time(1400 frames per second for 50 kHz excitation) with signal-noise-ratio above 62 dB and repeatability error below 0.7%.Static experiments have been conducted and the images manifested good resolution relative to the actual object distribution.The parallel ERT system has provided alternative experimental platform for the multiphase flow measurements by the dynamic experiments in terms of concentration and velocity.