Adaptive digital self-interference cancellation(ADSIC)is a significant method to suppress self-interference and improve the performance of the linear frequency modulated continuous wave(LFMCW)radar.Due to efficient im...Adaptive digital self-interference cancellation(ADSIC)is a significant method to suppress self-interference and improve the performance of the linear frequency modulated continuous wave(LFMCW)radar.Due to efficient implementation structure,the conventional method based on least mean square(LMS)is widely used,but its performance is not sufficient for LFMCW radar.To achieve a better self-interference cancellation(SIC)result and more optimal radar performance,we present an ADSIC method based on fractional order LMS(FOLMS),which utilizes the multi-path cancellation structure and adaptively updates the weight coefficients of the cancellation system.First,we derive the iterative expression of the weight coefficients by using the fractional order derivative and short-term memory principle.Then,to solve the problem that it is difficult to select the parameters of the proposed method due to the non-stationary characteristics of radar transmitted signals,we construct the performance evaluation model of LFMCW radar,and analyze the relationship between the mean square deviation and the parameters of FOLMS.Finally,the theoretical analysis and simulation results show that the proposed method has a better SIC performance than the conventional methods.展开更多
This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,th...This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter（DAC） mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications.展开更多
文摘Adaptive digital self-interference cancellation(ADSIC)is a significant method to suppress self-interference and improve the performance of the linear frequency modulated continuous wave(LFMCW)radar.Due to efficient implementation structure,the conventional method based on least mean square(LMS)is widely used,but its performance is not sufficient for LFMCW radar.To achieve a better self-interference cancellation(SIC)result and more optimal radar performance,we present an ADSIC method based on fractional order LMS(FOLMS),which utilizes the multi-path cancellation structure and adaptively updates the weight coefficients of the cancellation system.First,we derive the iterative expression of the weight coefficients by using the fractional order derivative and short-term memory principle.Then,to solve the problem that it is difficult to select the parameters of the proposed method due to the non-stationary characteristics of radar transmitted signals,we construct the performance evaluation model of LFMCW radar,and analyze the relationship between the mean square deviation and the parameters of FOLMS.Finally,the theoretical analysis and simulation results show that the proposed method has a better SIC performance than the conventional methods.
文摘This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter（DAC） mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications.
