An approach is proposed to realize a digital channelized receiver in the fractional Fourier domain （FRFD） for signal intercept applications. The presented architecture can be considered as a generalization of that i...An approach is proposed to realize a digital channelized receiver in the fractional Fourier domain （FRFD） for signal intercept applications. The presented architecture can be considered as a generalization of that in the traditional Fourier domain. Since the linear frequency modulation （LFM） signal has a good energy concentration in the FRFD, by choosing an appropriate fractional Fourier transform （FRFT） order, the presented architecture can concentrate the broadband LFM signal into only one sub-channel and that will prevent it from crossing several sub-channels. Thus the performance of the signal detection and parameter estimation after the sub-channel output will be improved significantly. The computational complexity is reduced enormously due to the implementation of the polyphase filter bank decomposition, thus the proposed architecture can be realized as efficiently as in the Fourier domain. The related simulation results are presented to verify the validity of the theories and methods involved in this paper.展开更多
A novel efficient partial sharing channelization structure with odd and even stacking is designed and implemented. There are two special designs in the proposed structure. Firstly, by the intensive channel overlap des...A novel efficient partial sharing channelization structure with odd and even stacking is designed and implemented. There are two special designs in the proposed structure. Firstly, by the intensive channel overlap design, for non-cooperative wideband signals, the proposed structure can achieve good parameter estimation accuracy and high probability of complete interception.Secondly, based on the partial sharing design developed in this paper, the computation burden of the proposed structure can be greatly reduced compared with the traditional directly implemented structures. Experiments and numerical simulations are conducted to evaluate the proposed structure, which shows its improvements over traditional methods in terms of field programmable gate arrays(FPGA) resource consumption and parameter estimation accuracy.展开更多
基金supported by the Program for New Century Excellent Talents in University(NCET-06-0921)
文摘An approach is proposed to realize a digital channelized receiver in the fractional Fourier domain （FRFD） for signal intercept applications. The presented architecture can be considered as a generalization of that in the traditional Fourier domain. Since the linear frequency modulation （LFM） signal has a good energy concentration in the FRFD, by choosing an appropriate fractional Fourier transform （FRFT） order, the presented architecture can concentrate the broadband LFM signal into only one sub-channel and that will prevent it from crossing several sub-channels. Thus the performance of the signal detection and parameter estimation after the sub-channel output will be improved significantly. The computational complexity is reduced enormously due to the implementation of the polyphase filter bank decomposition, thus the proposed architecture can be realized as efficiently as in the Fourier domain. The related simulation results are presented to verify the validity of the theories and methods involved in this paper.
文摘A novel efficient partial sharing channelization structure with odd and even stacking is designed and implemented. There are two special designs in the proposed structure. Firstly, by the intensive channel overlap design, for non-cooperative wideband signals, the proposed structure can achieve good parameter estimation accuracy and high probability of complete interception.Secondly, based on the partial sharing design developed in this paper, the computation burden of the proposed structure can be greatly reduced compared with the traditional directly implemented structures. Experiments and numerical simulations are conducted to evaluate the proposed structure, which shows its improvements over traditional methods in terms of field programmable gate arrays(FPGA) resource consumption and parameter estimation accuracy.
