A high precision time-to-digital converter based on multi-phase clock implemented within Field-Programmable-Gate-Array

In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.

Clock distribution and local oscillator of a digital low-level radio-frequency board for SSRF

In the storage ring RF system of Shanghai Synchrotron Radiation Facility,the clock distribution and the local oscillator are two parts of the digital low level radio frequency hardware board.In this paper,we designed and produced the clock distribution and the local oscillator board using the AD9858 and AD9510 chips.The results show that the phase noise of the local oscillator signal is lower than 100dBc/Hz with 50 kHz offset.

Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters: State-of-the-Art and a Design Example

This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.

Design of Digital Circuit Experiment Course Based on FPGA

With the development of integrated circuit, the content of digital circuit experiment course is constantly updated. In order to keep up with the development trend of the Times and make students’ professional knowledge meet the needs of the industry, the school adopts the FPGA experimental platform to carry out teaching reform from the two aspects of platform and experiment, and carry out reasonable experimental planning to enrich the experimental content. In this paper, the traditional knowledge points of logic algebra, trigger, timer, counter, decoder and digital tube are organically combined, and the digital clock system is designed and realized. The practice shows that the combination of modern design method and traditional digital circuit teaching method can play a good teaching effect. In this way, students can also fully learn, understand and skillfully use the new technology in the experiment, and in the process of building a comprehensive understanding of digital circuits.

Analog-to-digital conversion of information in the retina

We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.

基于时钟抖动流水线结构的高效率真随机数发生器

现代加密系统对密钥随机性的需求不断增加。使用时序抖动、热噪声、亚稳态等作为熵源的真随机数发生器,因其可以提供高质量的随机性成为该领域的研究热点。因此,提出一种可配置、轻量级、高效率的真随机数发生器。该发生器使用基于随机数学模型的设计方法,由差分构架的两级时钟抖动流水线组成。第一级流水线中两个环形振荡器在规定时间内累积抖动,第二级流水线利用近似相同的两个环形振荡器的微小周期差构建时间数字转换器,对第一级输出的高斯抖动进行量化,通过数字化模块输出随机比特。在时间数字转换器运行过程中,第一级流水线已经重新启动累积下一个阶段的抖动,减少了空闲时间,提高了真随机数的质量和效率。在Xilinx Atrix-7平台进行了验证,该结构的硬件资源仅消耗了25个LUTs和13个DFFs,获得高达32.55 Mb/s的吞吐量。

宋代水运仪象台图像复刻与虚拟展示设计

提升宋代水运仪象台虚拟展示设计的沉浸性、交互性。实地调研、测绘,将三维建模和动画、360全息投影等三维数字化技术应用于水运仪象台的虚拟展陈。真实复刻出其虚拟模型,呈现出虚拟立体的数字图像,完整且清晰地展示了其外观构造和内部结构及机械运转状态。数字化技术为展示水运仪象台的千年风貌提供了新的方式,对于中华文明史上杰出科技的保存与传播有积极的借鉴意义。

面向数字时钟调相的高精度低跃变控制码设计

面向数字时钟调相系统,提出了一种相位插值控制码匹配方法,减少了相邻相位之间控制码变化的位数,减小了相位误差和幅度跃变。通过迭代的思想,同时平衡控制码跳变所带来的误差与相位调整之间的转换关系,并行考虑控制码对输出信号幅度的影响,实现相位误差更小的电路结构。仿真结果表明,在文中的控制码调相下,电路输出时钟信号的幅度跃变小于6%。

基于先进CMOS工艺的多通道Gbps LVDS接收器

在SIP(System In a Package)系统中集成具有LVDS(Low-Voltage Differential Signal)接口的多通道高速模数转换器(Analog-to-Digital Converter,ADC)时,面临不同LVDS输出通道延时不同所导致的数据采集错误的问题,为此设计了一个多通道自适应LVDS接收器。通过采用数据时钟恢复技术产生一个多相位的采样时钟,并结合ADC的测试模式来确认每一个通道的采样相位,能够自动对每一个通道的延时分别进行调整,以达到对齐各通道采样相位点,保证数据正确采集的目的。最后,基于先进CMOS工艺进行了接收器的设计、仿真、后端设计实现和流片测试,仿真和流片后的板级测试结果均表明该接收器能够对通道延迟进行自动调节以对齐采样相位,且最大的采样相位调节范围为±3 bit,信噪比大于65 dB,满足了设计要求和应用需求。

AM信号数字解调在原子钟误差处理中的应用探讨

目前所有的原子频标都是基于原子或者离子的共振跃迁而实现的,利用了量子能级间跃迁的标准频率。在我国目前得到大量工程应用的微波原子钟之一为氢脉泽原子钟,其拥有异常出色的长期频率稳定度。精确地测定原子的频率,则需要对氢脉泽信号进行处理。由此引出探讨一种方法,是如何将基于被动型双频探测机理的氢脉泽信号,以及原子钟相应的微波腔频率控制信号通过数字解调的方式提取出来,经过数模采样后通过软件算法反馈实现伺服控制,锁定后输出稳定基准频率源。

基于SDH的电力通信网络中的时钟同步机制研究与性能评估

文章针对基于同步数字体系(Synchronous Digital Hierarchy,SDH)的电力通信网络中的时钟同步机制展开研究与性能评估。通过分析SDH电力通信网络的基础知识和时钟同步需求,设计一种有效的时钟同步机制,并提出相应的同步算法和优化方法。在此基础上,建立评估性能的方法与实验平台,并对实验结果进行深入的分析与评估。通过文章的研究,为提升SDH电力通信网络中时钟同步的性能提供重要参考。

Design of a Low Power DSP with Distributed and Early Clock Gating

A novel clock structure of a low-power 16-bit very large instruction word (VLIW) digital signal processor (DSP) was proposed. To improve deterministic clock gating and to solve the drawback of conventional clock gating circuit in high speed circuit, a distributed and early clock gating method was developed on its instruction fetch & decoder unit, its pipelined data-path unit and its super-Harvard memory interface unit. The core was implemented following the Synopsys back-end flow under TSMC (Taiwan Silicon manufacture corporation) 0.18-μm 1.8-V 1P6M process, with a core size of 2 mm×2 mm. Result shows that it can run under 200 MHz with a power performance around 0.3 mW/MIPS. Meanwhile, only 39.7% circuit is active simultaneously in average, compared to its non-gating counterparts.

相控-延时链混合架构时间数字转换器

高精度时间间隔测量过程中,为兼顾测量分辨和精度的同时,简化校准过程,提出一种混合架构的时间数字转换器(TDC)设计方法。该方法将相控时钟架构与抽头延时链(TDL)架构结合,利用不同相位的时钟对抽头延时链实现并行采样,一次测量过程中可以得到多个测量值,最后利用多个测量值的均值表示测量结果。该方法在Kintex-7 FPGA上进行实验测试,结果表明在进行简单校准的情况下,仍然可以保持较高的测量分辨率和精度,从而证明提出方法的有效性与可行性。

镱离子光钟的多波长数字PID激光稳频系统

针对镱离子光钟实验中激光冷却并操控离子时,激光器频率漂移影响原子钟系统的问题,基于数字PID控制方法,设计了一种新的多通道频率-数字信号转换稳频方法,将多路多波长激光频率锁定在波长计的参考频率上。对激光器锁定前和锁定后的频率进行一定时长的数据采集及数据对比,激光频率漂移由800 MHz控制在±0.8 MHz,激光频率稳定度由9.29×10^(-10)@1 s优化至2.79×10^(-10)@1 s,频率千秒稳达到3.85×10^(-12)。该系统简单、易实现,具有小型化、适应性强的优点。

车载日历时钟及温度测量系统

以AT89S52单片机为核心,设计一种智能车载日历时钟及温度测量系统.系统主要包括日历时钟、温度检测、按键、显示等部分.系统采用时钟电路芯片实现时钟的实时显示功能,并采用温度传感器实现环境温度的采集和A/D信号的转换,再通过单片机将其送入数码管进行显示.利用Proteus和Keil软件对系统进行仿真,结果表明该系统可实现预期功能.与传统的温度测量系统相比,该系统能够快速检测并反映在数码管上,测量精度高(测量精度为±0.5℃)且读数方便,具有很强的实用性和通用性.

以数字钟电路的设计为例开展研讨式教学

电工电子学是工科非电类专业的专业基础课,随着新时期人才培养方案的调整,要在较少的学时内讲授完所有内容,同时兼顾培养学员解决实际问题的能力,是一个很大的挑战。本文针对非电类专业学生的特点,以设计数字钟电路为例开展研讨式教学,让学生深入学习情境中去,将“教”与“学”融为一体,使学生在实际应用中巩固和加深理论知识。

数字化变电站中高精度同步采样时钟的设计

在数字化变电站的应用中,对同步采样时钟要求高稳定和高精度,其实现关键在于消除同步采样时钟的误差。文中从分析同步采样时钟误差产生的原因出发,利用全球定位系统(GPS)接收机输出GPS时钟误差分布的特点和晶振频率在短时间内的相对稳定性及现场可编程门阵列(FPGA)的高速数字信号处理的特性,采用相应处理措施消除了晶振频率偏差对同步采样时钟的影响,实现了GPS时钟在短时间内出现较大偏移或扰动时对其进行人为补偿,从而保证了采样时钟的精确同步,为数字化变电站的设计应用提供了一种高稳定、高精度的同步采样时钟设计方法。

光电跟踪设备数字视频图像信息光纤传输系统设计

为提高光电跟踪设备中数字视频图像信息的传输带宽,增强图像传输抗电磁干扰能力并减轻导电环配线工作量,开发了应用于光电跟踪设备的数字视频图像信息光纤传输系统。利用光纤传输抗干扰性强、带宽高等优势改善了数字视频图像信息的传输质量,增大了数据传输的容量。在发送端将并行的数字视频信息串行化,提供给光纤模块,电信号转换为光信号,通过光纤传输到接收端;在接收端光纤模块将光信号还原为高速的电信号,再经解串行化还原为原有的数据格式。场同步、行同步以及数据信息组合传输,经处理的时钟信号作为全局时钟单独传输。实验结果表明:利用光纤传输高速数字视频信息,图像正确,带宽达到1.25 Gbit,相机时钟频率可达62.5 MHz,数据传输延时为222 ns左右,最大为236 ns,时钟信号的边沿可对齐数据的有效位置。

基于FPGA的时间间隔测量系统的设计

为了解决电容充放电放大电路测量时间间隔的不稳定,采用复杂可编程芯片FPGA设计实现精密时间间隔的测量。FPGA的锁相环(PLL)电路得到高频时钟,时钟管理器(DCM)实现高速时钟移相,产生的内插时钟得到高精度时间测量。通过在光电回波脉冲时间间隔测量系统中验证,该设计可以得到200ps的时间间隔测量精度。采用FPGA芯片设计的粗和细数字化测量系统,具有集成度高,性能稳定,抗干扰强,设计方便等优点,能广泛应用于科研和生产中。

满足IEC61850要求的站用时钟服务器

基于IEC61850标准体系的数字化变电站,要求时钟提供SNTP软件授时和光脉冲硬件对时。提出了利用GPS接收器与FPGA+CPU微机系统实现时钟服务器方案。其中FPGA实现脉冲信号硬件对时,CPU系统实现SNTP协议软件授时,CPU与FPGA间通过数据总线联系,传递显示时间、IRIG-B码数据和同步状态等信息。详细介绍了时钟的授时原理、硬件设计、软件实现以及守时功能。该时钟服务器满足了IEC61850的要求,守时精度达到晶振稳定度水平。