An analog/digital reconfigurable automatic gain control （AGC） circuit with a novel DC offset cancel- lation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to...An analog/digital reconfigurable automatic gain control （AGC） circuit with a novel DC offset cancel- lation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips. What＇s more, a novel DC offset cancellation （DCOC） circuit with an HPCF （high pass cutoff frequency） less than 10 kHz is proposed. The AGC is fabricated by a 0.18μm CMOS process. Under analog control mode, the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz. Under digital control mode, through a 5-bit digital control word, the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB. The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV, while the offset voltage of 40 mV is introduced into the input. The overall power consumption is less than 3.5 mA, and the die area is 800 ×300μm2.展开更多
The digital proportion control is introduced to improve the performance of the analog adaptive interference cancellation system （ICS）. For the high frequency parts of the signals after multiplier are not required,th...The digital proportion control is introduced to improve the performance of the analog adaptive interference cancellation system （ICS）. For the high frequency parts of the signals after multiplier are not required,the sampling frequency need not satisfy the sampling theorem for high frequency. Because the sampling,calculation and output expend time in digital control,the ideal condition,delay condition and delay-wait condition are taken into account. Through analyzing the system model with three conditions,we gain the stable conditions of the system,the optimization step factors that can make the system converge fastest and the formulas of the interference cancellation ratios （ICRs）. One step convergence can be accomplished under ideal condition,whereas the system can not converge in one step under delay condition and delay-wait condition. The calculation results show the convergence speed of delay-wait condition is slower than that of delay condition. The ICR is improved with the increase of the step factor which is in stable bound,but the convergence speed is decreased if the step factor exceeds the optimization step factor. In order to avoid that confine,the method of amending the steady state weight to improve the ICR is proposed. The analyses are in agreement with the computer simulations.展开更多
基金Project supported by the Major Projects for the Core Electronic Devices,High-End General Chips and Basic Software Products(No. 2009ZX01031-002-008)
文摘An analog/digital reconfigurable automatic gain control （AGC） circuit with a novel DC offset cancel- lation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips. What＇s more, a novel DC offset cancellation （DCOC） circuit with an HPCF （high pass cutoff frequency） less than 10 kHz is proposed. The AGC is fabricated by a 0.18μm CMOS process. Under analog control mode, the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz. Under digital control mode, through a 5-bit digital control word, the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB. The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV, while the offset voltage of 40 mV is introduced into the input. The overall power consumption is less than 3.5 mA, and the die area is 800 ×300μm2.
文摘The digital proportion control is introduced to improve the performance of the analog adaptive interference cancellation system （ICS）. For the high frequency parts of the signals after multiplier are not required,the sampling frequency need not satisfy the sampling theorem for high frequency. Because the sampling,calculation and output expend time in digital control,the ideal condition,delay condition and delay-wait condition are taken into account. Through analyzing the system model with three conditions,we gain the stable conditions of the system,the optimization step factors that can make the system converge fastest and the formulas of the interference cancellation ratios （ICRs）. One step convergence can be accomplished under ideal condition,whereas the system can not converge in one step under delay condition and delay-wait condition. The calculation results show the convergence speed of delay-wait condition is slower than that of delay condition. The ICR is improved with the increase of the step factor which is in stable bound,but the convergence speed is decreased if the step factor exceeds the optimization step factor. In order to avoid that confine,the method of amending the steady state weight to improve the ICR is proposed. The analyses are in agreement with the computer simulations.
