Digital receivers have become more and more popular in radar, communication, and electric warfare for the advantages compared with their analog counterparts. But conventional digital receivers have been generally cons...Digital receivers have become more and more popular in radar, communication, and electric warfare for the advantages compared with their analog counterparts. But conventional digital receivers have been generally considered impractical for bandwidth greater than several hundreds MHz. To extend receiver bandwidth, decrease data rate and save hardware resources, three novel structures are proposed. They decimate the data stream prior to mixing and filtering, then process the multiple decimated streams in parallel at a lower rate. Consequently it is feasible to realize wideband receivers on the current ASIC devices. A design example and corresponding simulation results are demonstrated to evaluate the proposed structures.展开更多
A cueing wideband digital Electronic Warfare （EW） receiver is presented. The proposed receiver, which is to measure the instantaneous frequency and bandwidth of the intercept short-duration pulse radar signals that ...A cueing wideband digital Electronic Warfare （EW） receiver is presented. The proposed receiver, which is to measure the instantaneous frequency and bandwidth of the intercept short-duration pulse radar signals that cue and match the corresponding ones, meets the requirements of good sensitivity and dynamic range for EW and can save hardware resources greatly as well. In addition, real-time signal processing, which is the main bottleneck for covering a wide instantaneous frequency band for EW receiver, is better solved in the proposed design structure. The highly efficient implementation and good parameter estimation algorithms are proposed as welL Theoretical analysis and experimental results show that this structure is feasible.展开更多
数字接收系统中,对输入的射频信号直接中频采样后进行数字下变频(Digital Down Converter,DDC),有效减少了硬件模拟设备的数量,提高了系统的可靠性和稳定性。针对高速数字下变频存在的采样率高、资源消耗高等难点,利用滤波器系数的对称...数字接收系统中,对输入的射频信号直接中频采样后进行数字下变频(Digital Down Converter,DDC),有效减少了硬件模拟设备的数量,提高了系统的可靠性和稳定性。针对高速数字下变频存在的采样率高、资源消耗高等难点,利用滤波器系数的对称性特点设计了一种在不降低处理速度的前提下,减少现场可编程门阵列(Field ProgrammableGate Array,FPGA)内部处理单元个数,实现功耗降低的有限冲击响应(Finite Impulse Response,FIR)滤波器,并在FPGA中得到了实现。实验结果表明,该方法性能优异,可大幅节省资源,具有较高的工程实用价值。展开更多
电能计量表在使用过程中出现故障,会导致电力消耗情况记录精准度降低。为了避免该现象的发生,提出基于直接数字控制(direct digital control,DDC)的电能计量装置现场检验方法。依据电能计量装置相关特点,处理电能计量装置现场数据。结合...电能计量表在使用过程中出现故障,会导致电力消耗情况记录精准度降低。为了避免该现象的发生,提出基于直接数字控制(direct digital control,DDC)的电能计量装置现场检验方法。依据电能计量装置相关特点,处理电能计量装置现场数据。结合DDC技术,设计配变关口现场检验数据取证过程,通过前期准备、误差值确定和误差处理完成配变关口现场检验。设计互感器负荷现场检验数据取证过程,完成互感器负荷现场检验。在DDC支持下,设计信息隐藏模型。经实验验证:随着检验时间不断增加,无故障状态下所提方法检验精准度高于85%,在互感器故障情况下所提方法检验精准度最高为88%。展开更多
The relationship between the hardware requirement of digital down converters（DDCs）in ultra-low symbol rate receivers and the word length is studied.Through analyzing the impact of word length selection to the system...The relationship between the hardware requirement of digital down converters（DDCs）in ultra-low symbol rate receivers and the word length is studied.Through analyzing the impact of word length selection to the system performance,a modified scheme is presented to decline the resource consumption without too much degradation on the signal to noise ratio（SNR）.Theoretical analysis and numerical results demonstrate that compared to the traditional design,the proposed scheme could save dozens of memory resources.The scheme also includes some selectable parameters to achieve desired performance in various circumstances.Different from previous work in DDCs that concentrates mostly on the structure design,this paper considers special applications such as ultra-low symbol rate receivers.展开更多
基金This project was supported by the National Defense I mportant Research Foundation of China(03413070506)
文摘Digital receivers have become more and more popular in radar, communication, and electric warfare for the advantages compared with their analog counterparts. But conventional digital receivers have been generally considered impractical for bandwidth greater than several hundreds MHz. To extend receiver bandwidth, decrease data rate and save hardware resources, three novel structures are proposed. They decimate the data stream prior to mixing and filtering, then process the multiple decimated streams in parallel at a lower rate. Consequently it is feasible to realize wideband receivers on the current ASIC devices. A design example and corresponding simulation results are demonstrated to evaluate the proposed structures.
基金Supported by the National Defense Pre-research Fund of China
文摘A cueing wideband digital Electronic Warfare （EW） receiver is presented. The proposed receiver, which is to measure the instantaneous frequency and bandwidth of the intercept short-duration pulse radar signals that cue and match the corresponding ones, meets the requirements of good sensitivity and dynamic range for EW and can save hardware resources greatly as well. In addition, real-time signal processing, which is the main bottleneck for covering a wide instantaneous frequency band for EW receiver, is better solved in the proposed design structure. The highly efficient implementation and good parameter estimation algorithms are proposed as welL Theoretical analysis and experimental results show that this structure is feasible.
文摘电能计量表在使用过程中出现故障,会导致电力消耗情况记录精准度降低。为了避免该现象的发生,提出基于直接数字控制(direct digital control,DDC)的电能计量装置现场检验方法。依据电能计量装置相关特点,处理电能计量装置现场数据。结合DDC技术,设计配变关口现场检验数据取证过程,通过前期准备、误差值确定和误差处理完成配变关口现场检验。设计互感器负荷现场检验数据取证过程,完成互感器负荷现场检验。在DDC支持下,设计信息隐藏模型。经实验验证:随着检验时间不断增加,无故障状态下所提方法检验精准度高于85%,在互感器故障情况下所提方法检验精准度最高为88%。
基金Supported by the National Natural Science Foundation of China(60972018)
文摘The relationship between the hardware requirement of digital down converters（DDCs）in ultra-low symbol rate receivers and the word length is studied.Through analyzing the impact of word length selection to the system performance,a modified scheme is presented to decline the resource consumption without too much degradation on the signal to noise ratio（SNR）.Theoretical analysis and numerical results demonstrate that compared to the traditional design,the proposed scheme could save dozens of memory resources.The scheme also includes some selectable parameters to achieve desired performance in various circumstances.Different from previous work in DDCs that concentrates mostly on the structure design,this paper considers special applications such as ultra-low symbol rate receivers.
