Status quo and future trends of 2015children’s publications released by the Shanghai Press and Publication shows that in the past decade,the domestic children’s book market is developing rapidly with an average annu...Status quo and future trends of 2015children’s publications released by the Shanghai Press and Publication shows that in the past decade,the domestic children’s book market is developing rapidly with an average annual growth of 10%.Children’s books are seeing an increasing ratio with a market share of over 40%.展开更多
Automatic gain control (AGC) has been used in many applications. The key features of AGC, including a steady state output and static/dynamic timing response, depend mainly on key parameters such as the reference and...Automatic gain control (AGC) has been used in many applications. The key features of AGC, including a steady state output and static/dynamic timing response, depend mainly on key parameters such as the reference and the filter coefficients. A simple model developed to describe AGC systems based on several simple assumptions shows that AGC always converges to the reference and that the timing constant depends on the filter coefficients. Measures are given to prevent oscillations and limit cycle effects. The simple AGC system is adapted to a multiple AGC system for a TV tuner in a much more efficient model. Simulations using the C language are 16 times faster than those with MATLAB, and 10 times faster than those with a mixed register transfer level (RTL)-simulation program with integrated circuit emphasis (SPICE) model.展开更多
This paper describes a fast digital calibration scheme for pipelined analog-to-digital converters(ADCs). The proposed method corrects the nonlinearity caused by finite opamp gain and capacitor mismatch in multiplyin...This paper describes a fast digital calibration scheme for pipelined analog-to-digital converters(ADCs). The proposed method corrects the nonlinearity caused by finite opamp gain and capacitor mismatch in multiplying digital-to-analog converters(MDACs).The considered calibration technique takes the advantages of both foreground and background calibration schemes.In this combination calibration algorithm,a novel parallel background calibration with signal-shifted correlation is proposed,and its calibration cycle is very short.The details of this technique are described in the example of a 14-bit 100 Msample/s pipelined ADC.The high convergence speed of this background calibration is achieved by three means.First,a modified 1.5-bit stage is proposed in order to allow the injection of a large pseudo-random dithering without missing code.Second,before correlating the signal,it is shifted according to the input signal so that the correlation error converges quickly.Finally,the front pipeline stages are calibrated simultaneously rather than stage by stage to reduce the calibration tracking constants.Simulation results confirm that the combination calibration has a fast startup process and a short background calibration cycle of 2×2^(21) conversions.展开更多
Facing the body's EEG(electroencephalograph, 0.5–100 Hz, 5–100 μV) and ECG's(electrocardiogram,〈 100 Hz, 0.01–5 mV) micro signal detection requirement, this paper develops a pervasive application micro sign...Facing the body's EEG(electroencephalograph, 0.5–100 Hz, 5–100 μV) and ECG's(electrocardiogram,〈 100 Hz, 0.01–5 mV) micro signal detection requirement, this paper develops a pervasive application micro signal detection ASIC chip with the chopping modulation/demodulation method. The chopper-stabilization circuit with the RRL(ripple reduction loop) circuit is to suppress the ripple voltage, which locates at the single-stage amplifier's outputting terminal. The single-stage chopping core's noise has been suppressed too, and it is beneficial for suppressing noises of post-circuit. The chopping core circuit uses the PFB(positive feedback loop) to increase the inputting resistance, and the NFB(negative feedback loop) to stabilize the 40 dB intermediate frequency gain. The cascaded switch-capacitor sample/hold circuit has been used for deleting spike noises caused by non-ideal MOS switches, and the VGA/BPF(voltage gain amplifier/band pass filter) circuit is used to tune the chopper system's gain/bandwidth digitally. Assisted with the designed novel dry-electrode, the real test result of the chopping amplifying circuit gives some critical parameters: 8.1 μW/channel, 0.8 μVrms(@band-widthD100 Hz), 4216–11220 times digitally tuning gain range, etc. The data capture system uses the NI CO's data capturing DAQmx interface,and the captured micro EEG/ECG's waves are real-time displayed with the PC-Labview. The proposed chopper system is a unified EEG/ECG signal's detection instrument and has a critical real application value.展开更多
文摘Status quo and future trends of 2015children’s publications released by the Shanghai Press and Publication shows that in the past decade,the domestic children’s book market is developing rapidly with an average annual growth of 10%.Children’s books are seeing an increasing ratio with a market share of over 40%.
基金Supported by the National Natural Science Foundation of China (No. 60572087)
文摘Automatic gain control (AGC) has been used in many applications. The key features of AGC, including a steady state output and static/dynamic timing response, depend mainly on key parameters such as the reference and the filter coefficients. A simple model developed to describe AGC systems based on several simple assumptions shows that AGC always converges to the reference and that the timing constant depends on the filter coefficients. Measures are given to prevent oscillations and limit cycle effects. The simple AGC system is adapted to a multiple AGC system for a TV tuner in a much more efficient model. Simulations using the C language are 16 times faster than those with MATLAB, and 10 times faster than those with a mixed register transfer level (RTL)-simulation program with integrated circuit emphasis (SPICE) model.
基金supported by the National Key Project,China(No.2008zx010200001)
文摘This paper describes a fast digital calibration scheme for pipelined analog-to-digital converters(ADCs). The proposed method corrects the nonlinearity caused by finite opamp gain and capacitor mismatch in multiplying digital-to-analog converters(MDACs).The considered calibration technique takes the advantages of both foreground and background calibration schemes.In this combination calibration algorithm,a novel parallel background calibration with signal-shifted correlation is proposed,and its calibration cycle is very short.The details of this technique are described in the example of a 14-bit 100 Msample/s pipelined ADC.The high convergence speed of this background calibration is achieved by three means.First,a modified 1.5-bit stage is proposed in order to allow the injection of a large pseudo-random dithering without missing code.Second,before correlating the signal,it is shifted according to the input signal so that the correlation error converges quickly.Finally,the front pipeline stages are calibrated simultaneously rather than stage by stage to reduce the calibration tracking constants.Simulation results confirm that the combination calibration has a fast startup process and a short background calibration cycle of 2×2^(21) conversions.
基金Project supported by the National Natural Science Foundation of China(Nos.61527815,31500800,61501426,61471342)the National Key Basic Research Plan(No.2014CB744600)+1 种基金the Beijing Science and Technology Plan(No.Z141100000214002)the Chinese Academy of Sciences’Key Project(No.KJZD-EW-L11-2)
文摘Facing the body's EEG(electroencephalograph, 0.5–100 Hz, 5–100 μV) and ECG's(electrocardiogram,〈 100 Hz, 0.01–5 mV) micro signal detection requirement, this paper develops a pervasive application micro signal detection ASIC chip with the chopping modulation/demodulation method. The chopper-stabilization circuit with the RRL(ripple reduction loop) circuit is to suppress the ripple voltage, which locates at the single-stage amplifier's outputting terminal. The single-stage chopping core's noise has been suppressed too, and it is beneficial for suppressing noises of post-circuit. The chopping core circuit uses the PFB(positive feedback loop) to increase the inputting resistance, and the NFB(negative feedback loop) to stabilize the 40 dB intermediate frequency gain. The cascaded switch-capacitor sample/hold circuit has been used for deleting spike noises caused by non-ideal MOS switches, and the VGA/BPF(voltage gain amplifier/band pass filter) circuit is used to tune the chopper system's gain/bandwidth digitally. Assisted with the designed novel dry-electrode, the real test result of the chopping amplifying circuit gives some critical parameters: 8.1 μW/channel, 0.8 μVrms(@band-widthD100 Hz), 4216–11220 times digitally tuning gain range, etc. The data capture system uses the NI CO's data capturing DAQmx interface,and the captured micro EEG/ECG's waves are real-time displayed with the PC-Labview. The proposed chopper system is a unified EEG/ECG signal's detection instrument and has a critical real application value.