Highly efficient class-F power amplifier with digital predistortion for WCDMA applications

A digital predistorted class-F power amplifier （PA） using Cree GaN HEMT CGH40010 operating at 2. 12 GHz is presented to obtain high efficiency and excellent linearity for wideband code-division multiple access （ WCDMA ） applications. Measurement results with the continuous wave （CW） signals indicate that the designed class-F PA achieves a peak power-added efficiency （PAE） of 75. 2% with an output power of 39.4 dBm. The adjacent channel power ratio （ACPR） of the designed PA after digital predistortion （DPD） decreases from -28. 3 and -27. 5 dBc to -51.9 and -54. 0 dBc, respectively, for a 4-carrier 20 MHz WCDMA signal with 7. 1 dB peak to average power ratio （PAPR）. The drain efficiency （DE） of the PA is 37. 8% at an average output power of 33. 3 dBm. The designed power amplifier can be aoolied in the WCDMA system.

Adaptive Digital Predistortion Schemes to Linearize RF Power Amplifiers with Memory Effects

To compensate for nonlinear distortion introduced by RF power amplifiers （PAs） with memory effects, two correlated models, namely an extended memory polynomial （EMP） model and a memory lookup table （LUT） model, are proposed for predistorter design. Two adaptive digital predistortion （ADPD） schemes with indirect learning architecture are presented. One adopts the EMP model and the recursive least square （RLS） algorithm, and the other utilizes the memory LUT model and the least mean square （LMS） algorithm. Simulation results demonstrate that the EMP-based ADPD yields the best linearization performance in terms of suppressing spectral regrowth. It is also shown that the ADPD based on memory LUT makes optimum tradeoff between performance and computational complexity.

Robust Digital Predistortion for LTE/5G Power Amplifiers Utilizing Negative Feedback Iteration

A robust digital predistortion(DPD)technique utilizing negative feedback iteration is introduced for linearizing power amplifiers(PAs)in long term evolution(LTE)/5G systems.Different from the conventional direct learning and indirect learning structure,the proposed DPD suggests a two-step method to identify the predistortion.Firstly,a negative feedback based iteration is used to estimate the optimal DPD signal.Then the corresponding DPD parameters are extracted by forward modeling with the input signal and optimal DPD signal.The iteration can be applied to both single-band and dual-band PAs,which will achieve superior linear performance than the conventional direct learning DPD while having a relatively low computational complexity.The measurement is carried out on a broadband Doherty PA(DPA)with a 200 MHz bandwidth LTE signal at 2.1 GHz,and on a 5G DPA with two 10 MHz LTE signals at 3.4/3.6 GHz for validation in dual-band scenarios.

Low Noise Amplifier Design for Digital Television Applications

The DVB-T (Digital Video Broadcasting—Terrestrial) standard is being deployed in many parts of the world for digital broadcasting services, providing a variety of features extending the capabilities of the older analog ones. In this paper, a two-stage low noise amplifier (LNA) is designed for use with the DVB-T standard. The design is employed based on microstrip. The microwave design meets all the specifications required, achieving input and output return loss below ?10 dB, high gain of 35 dB and high linearity. Low noise figure of 1.3 dB is achieved with the use of pHEMT transistor technology.

Digital Lock-in Amplifier Based on Microcontroller

A method of implementing high cost-effective and highly integrated digital lock-in amplifier with microcontroller is discussed. And the digital lock-in amplifier is more suitable for meastwing lowfrequency weak signal. Digital signal sequence is obtained through sampling signal measured over an integer number of signal periods, but digital reference sequence is acquired through mathematical operation, then digital phase sensitive detection can be implemented by calculating the cross-correlation function of digital signal sequence and digital reference sequence. In addition, the frequency response and phase character of the digital lock-in amplifier is analyzed. Finally, the designed digital lock-in amplifier is achieved. Expermental results show that the digital lock-in amplifier can be used for measuring weak signal with low ignal-to-noise ratio.

Robust Digital Control of a Broadband PWM Power Amplifier

Lately, it is required that the bandwidth of PWM （pulse width modulation） power amplifier is extended. For example, it is in application of the testing power supply of a low frequency immunity examination, or a class-D amplifier. In this paper, the authors show that the bandwidth of PWM power amplifier can be controller. This controller is implemented on a DSP （digital can be made wider with this controller. extended by using an approximate 2DOF （2-degree-of-freedom） digital signal processor）. It is demonstrated from experiments that the bandwidth

Capacitance Sensing and Software-Realized Lock-in Amplifier for the Electromagnetically Levitated Micro Gyroscope

In the novel prototype of micro-gyroscope structure,the new configured capacitance sensing scheme for the micro gyroscope was analyzed and the virtual instrument based detection scheme was implemented.The digital lock-in amplifier was employed in the capacitance detection to restrain the noise interference.The capacitance analysis shows that 1 fF capacitance variation corresponds to 0.1 degree of the turn angle.The differential capacitance bridge and the charge integral amplifier were used as the front signal input interface.In the implementation of digital lock-in amplifier,a new routine which warranted the exactly matching of the reference phase to signal phase was proposed.The result of the experiment shows that digital lock-in amplifier can greatly eliminate the noise in the output signal.The non linearity of the turn angle output is 2.3% and the minimum resolution of turn angle is 0.04 degrees.The application of the software demodulation in the signal detection of micro-electro-mechanical-system(MEMS)device is a new attempt,and it shows the prospective for a high-performance application.

Design of Si-bipolar Monolithic Main Amplifier IC for Optical Fiber Receivers

A broadband amplifier with transadmittance and transimpedance stages is designed and two types of improved AGC amplifiers are developed on the base of theory study. Making use of the basic amplifier cells, a main amplifier IC for optical-fiber receivers is deliberated. By computer simulating the performances of the designed main amplifier meet the necessity of high gain and wide dynamic range . They are maximum voltage gain of 42 dB, the bandwidth of 730 MHz,the input signal( V p-p )range from 5 mV to 1 V,the output amplitude about 1 V, the dynamic range of 46 dB. The designed circuit containing no inductance and large capacitance will be convenient for realizing integration. A monolithic integrated design of 622 Mb/s main amplifier is completed.

A Strong Anti-Jamming Algorithm Based on FPGA for Estimating Loop Delay in Digital Predistortion System

At present what are the key points focused in the research of loop-delay estimation for the digital predistorter in the radio frequency （RF） power amplifier system is reducing its complexity of engineering realization and improving anti-jamming ability and computational speed. Besides, opening up its application scope should be contained. For these targets, a novel method including integer loop delay estimation and fractional part is proposed. The integer part applies amplitude-difference summation function and the fractional one adopts the method of finite impulse response （FIR） linear interpolation. The algorithm finds wide applications. What is more, strong anti-jamming ability and low complexity are also its merits. Simulation results support the above opinion. Digital predistortion （DPD） system based on this algorithm achieves good performance.

The Beijing network of digital geomagnetic pulsation observatories

We present herein an introduction to the Beijing network of digital geomagnetic pulsation observatories, and describe its essential features, and important roles in earthquake prediction studies and other geomagnetic investigations. The network provides digitalized data of geomagnetic events, such as magnetic storms, magnetic disturbances, geomagnetic daily variations, and geomagnetic pulsations. The digitalized data, convenient for processing and analysis, contain very rich information because of high accuracy and wide dynamic range of the instruments.

FPGA Implementation of a Power Amplifier Linearizer for an ETSI-SDR OFDM Transmitter

Most satellite digital radio （SDR） systems use orthogonal frequency-division multiplexing （OFDM） transmission, which means that variable envelope signals are distorted by the RF power amplifier （PA）. It is customary to back off the input power to the PA to avoid the PA nonlinear region of operation. In this way, linearity can be achieved at the cost of power efficiency. Another attractive option is to use a linearizer, which compensates for the nonlinear effects of the PA. In this paper, an OFDM transmitter conforming to European Telecommunications Standard Institute SDR Technical Specifications 2007-2008 was designed and implemented on a low-cost field-programmable gate array （FPGA） platform. A weakly nonlinear PA, operating in the L-band SDR frequency, was used for signal transmission. An adaptive linearizer was designed and implemented on the same FPGA device using digital predistortion to correct the undesired effects of the PA on the transmitted signal. Test results show that spectral distortion can be suppressed between 6-9 dB using the designed linearizer when the PA is driven close to its saturation region.

Fault Waveform Regenerator and Its Digital Closed-Loop Modification Technique

In order to provide a novel and more effective alternative to the commonly used relay protection testing device that outputs only the sinusoidal testing signals, the concept of fault waveform regenerator is proposed in this paper, together with its hardware structure and software flow chart. Fault waveform regenerator mainly depends on its power amplifiers (PAs) to regenerate the fault waveforms recorded by digital fault recorder (DFR). To counteract the PA’s inherent nonlinear distortions, a digital closed-loop modification technique that is different from the predistortion technique is conceived. And the experimental results verify the effectiveness of the fault waveform regenerator based on the digital closed-loop modification technique.

NONLINEAR CHARACTERIZATION OF CONCURRENT DUAL-BAND RF POWER AMPLIFIERS

In this paper, the synchronous concurrent dual-band RF signal is used to drive the RF Power Amplifier (PA). The nonlinear characterization of a concurrent dual-band RF PA is discussed while two band signals in the dual-band are modulated by CDMA2000 and WCDMA signals. When the two band signals in the dual-band of the PA are modulated with the same signals, it is found that the nonlinearity of the PA can be expressed by any of the two corresponding baseband data. On the other hand, when the two band signals in the dual-band of the PA are modulated with two different signals, the PA nonlinearity cannot be characterized by any of the two corresponding baseband data. In this case, its nonlinearity has to be denoted by a composite signals consisting of the two baseband signals. Consequently, the requirements for the speed of the A/D converter can be largely reduced. The experimental results with CDMA2000 and WCDMA signals demonstrate the speed of the A/D converter required is only 30 M Sample Per Second (SaPS), but it will be at least 70 M SaPS for the conventional method.

A Parallel Amplifier Structure for Increasing Dynamic Range of EW Receivers

In Electronic Warfare （EW） receivers, the desired Dynamic Range （DR） often far exceeds the dynamic range attainable with available Analog-to-Digital Converter （ADC） technology. ADC is the key bottleneck in achieving the needed dynamic range. In this paper, an approach for improving the effective DR by utiliTing multiple amplifiers is presented. The amplifiers, arranged in parallel channels with different gains, can increase the dynamic range greatly.

An RF power amplifier with inter-metal-shuffled capacitor for inter-stage matching in a digital CMOS process

One challenge of the implementation of fully-integrated RF power amplifiers into a deep submicro digital CMOS process is that no capacitor is available,especially no high density capacitor.To address this problem,a two-stage class-AB power amplifier with inter-stage matching realized by an inter-metal coupling capacitor is designed in a 180-nm digital CMOS process.This paper compares three structures of inter-metal coupling capacitors with metal-insulator-metal（MIM） capacitor regarding their capacitor density.Detailed simulations are carried out for the leakage,the voltage dependency,the temperature dependency,and the quality factor between an inter-metal shuffled（IMS） capacitor and an MIM capacitor.Finally,an IMS capacitor is chosen to perform the inter-stage matching.The techniques are validated via the design and implement of a two-stage class-AB RF power amplifier for an UHF RFID application.The PA occupies 370 × 200 μm^2 without pads in the 180-nm digital CMOS process and outputs 21.1 dBm with 40% drain efficiency and 28.1 dB power gain at 915 MHz from a single 3.3 V power supply.

A digitally controlled power amplifier with neutralization capacitors for Zigbee^(TM) applications

This paper presents a single chip CMOS power amplifier with neutralization capacitors for ZigbeeTM system according to IEEE 802.15.4. A novel structure with digital interface is adopted, which allows the output power ofa PA to be controlled by baseband signal directly, so there is no need for DAC. The neutralization capacitors will increase reverse isolation. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed power amplifier has a 13.5 dB power gain, 3.48 dBm output power and 35.1% PAE at P I dB point. The core area is 0.73 × 0.55 mm2.

Low-cost FPGA implementation of 2D digital pre-distorter for concurrent dual-band power amplifier

This paper proposes a low-cost hardware architecture based on concurrent dual-band digital pre-distorter （DPD）. The architecture is implemented on field programmable gate array （FPGA） to compensate for the nonlinearity of the concurrent dual-band power amplifier （PA）. This implementation introduces a novel model complexity reduction technique into system, namely, time-division multiplexing for out-of-band lookup tables （LUTs） sharing. Performances are evaluated with an experimental test setup using a wideband class-F PA. The dual-band signal center frequency separated by 80 MHz. Lower and upper center frequency are located at 2.61 GHz and 2.69 GHz, respectively. This novel DPD implementation maintains excellent performance, but uses hardware resources reduced by 29.17% compared with conventional approaches. The results show that the adjacent channel power ratio （ACPR） is less than -59 dBc and normalized mean square error （NMSE） is around - 62dB for lower sideband （LSB） and - 63dB for upper sideband （USB）.

Low Complexity Digital Pre-Distortion (DPD) for Multi-Band Radio over Fiber Transmission Systems

Nonlinear distortion is one of key limiting factors in radio over fiber (RoF) transmission systems. To suppress the nonlinear distortion, digital pre-distortion (DPD) has been investigated considerably. However, for multi-band signals, DPD becomes very complex, which limits the applications. To reduce the complexity, many simplified DPDs have been proposed. In this work, a new multidimensional DPD is proposed, in which in-band and out-of-band distortion are separated and the out-of-band distortion is evaluated by sum and differences of all input signals instead of all individual input signals, thus complexity is reduced. An up to 6-band 64-QAM orthogonal frequency division multiplexing (OFDM) signal with each bandwidth of 200 MHz in simulations and a 5-band 20 MHz 64-QAM OFDM signal in experiments are used to validate the pro-posed DPD. The validation is illustrated in the means of power spectrum, AM/AM and AM/PM distortion, and error vector magnitude (EVM) of the received signal constellations. The average EVM improvement by simulation for 3-band, 4-band, 5-band and 6-band signals is 19.97 dB, 18.65 dB, 16.64 dB and 15.44 dB, respectively. The average EVM improvement by experiments for 5-band signals is 8.1 dB. Considering the ten times of bandwidth difference, experiments and simulation agree well.

Beyond 200-Gb/s O-band intensity modulation and direct detection optics with joint look-uptable- based predistortion and digital resolution enhancement for low-cost data center interconnects

We propose a joint look-up-table(LUT)-based nonlinear predistortion and digital resolution enhancement scheme to achieve high-speed and low-cost optical interconnects using low-resolution digital-to-analog converters(DACs).The LUT-based predistortion is employed to mitigate the patterndependent effect(PDE)of a semiconductor optical amplifier(SOA),while the digital resolution enhancer(DRE)is utilized to shape the quantization noise,lowering the requirement for the resolution of DAC.We experimentally demonstrate O-band intensity modulation and direct detection(IM/DD)transmission of 124-GBd 4∕6-level pulse-amplitude modulation ePAMT-4∕6 and 112-GBd PAM-8 signals over a 2-km standard single-mode fiber(SSMF)with 3∕3.5∕4-bit DACs.In the case of 40-km SSMF transmission with an SOAbased preamplifier,124-GBd on-off-keying(OOK)/PAM-3/PAM-4 signals are successfully transmitted with 1.5∕2∕3-bit DACs.To the best of our knowledge,we have achieved the highest net data rates of 235.3-Gb∕s PAM-4,289.7-Gb∕s PAM-6,and 294.7 Gb∕s PAM-8 signals over 2-km SSMF,as well as 117.6-Gb∕s OOK,173.8-Gb∕s PAM-3,and−231.8 Gb∕s PAM-4 signals over 40-km SSMF,employing low-resolution DACs.The experimental results reveal that the joint LUT-based predistortion and DRE effectively mitigate the PDE and improve the signal-to-quantization noise ratio by shaping the noise.The proposed scheme can provide a powerful solution for low-cost IM/DD optical interconnects beyond 200 Gb∕s.

Design of a 10 bit high resolution,high speed time-to-digital converter using a two-step pulse-train time amplifier

A high resolution and fast conversion rate time-to-digital converter （TDC） design based on time amplifier （TA） is proposed. The pulse-train TA employs a two-step scheme. The input time interval is first amplified by a N-times TA and the effective time is extracted in pulse-train using a time-register. Then the resulted interval is further amplified by the other pulse-train amplifier to obtain the final result. The two-step TA can thus achieve large gain that is critical for high resolution TDC. Simulation results in 1.2 V, 65 nm technology showed that for a 10 bit TDC, a resolution of 0. 8 ps and a conversion rate of 150 MS/s are achieved while consuming 2. 1 mW power consumption.