Digital Lock-in Amplifier Based on Microcontroller

A method of implementing high cost-effective and highly integrated digital lock-in amplifier with microcontroller is discussed. And the digital lock-in amplifier is more suitable for meastwing lowfrequency weak signal. Digital signal sequence is obtained through sampling signal measured over an integer number of signal periods, but digital reference sequence is acquired through mathematical operation, then digital phase sensitive detection can be implemented by calculating the cross-correlation function of digital signal sequence and digital reference sequence. In addition, the frequency response and phase character of the digital lock-in amplifier is analyzed. Finally, the designed digital lock-in amplifier is achieved. Expermental results show that the digital lock-in amplifier can be used for measuring weak signal with low ignal-to-noise ratio.

Highly efficient class-F power amplifier with digital predistortion for WCDMA applications

A digital predistorted class-F power amplifier （PA） using Cree GaN HEMT CGH40010 operating at 2. 12 GHz is presented to obtain high efficiency and excellent linearity for wideband code-division multiple access （ WCDMA ） applications. Measurement results with the continuous wave （CW） signals indicate that the designed class-F PA achieves a peak power-added efficiency （PAE） of 75. 2% with an output power of 39.4 dBm. The adjacent channel power ratio （ACPR） of the designed PA after digital predistortion （DPD） decreases from -28. 3 and -27. 5 dBc to -51.9 and -54. 0 dBc, respectively, for a 4-carrier 20 MHz WCDMA signal with 7. 1 dB peak to average power ratio （PAPR）. The drain efficiency （DE） of the PA is 37. 8% at an average output power of 33. 3 dBm. The designed power amplifier can be aoolied in the WCDMA system.

Adaptive Digital Predistortion Schemes to Linearize RF Power Amplifiers with Memory Effects

To compensate for nonlinear distortion introduced by RF power amplifiers （PAs） with memory effects, two correlated models, namely an extended memory polynomial （EMP） model and a memory lookup table （LUT） model, are proposed for predistorter design. Two adaptive digital predistortion （ADPD） schemes with indirect learning architecture are presented. One adopts the EMP model and the recursive least square （RLS） algorithm, and the other utilizes the memory LUT model and the least mean square （LMS） algorithm. Simulation results demonstrate that the EMP-based ADPD yields the best linearization performance in terms of suppressing spectral regrowth. It is also shown that the ADPD based on memory LUT makes optimum tradeoff between performance and computational complexity.

Robust Digital Predistortion for LTE/5G Power Amplifiers Utilizing Negative Feedback Iteration

A robust digital predistortion(DPD)technique utilizing negative feedback iteration is introduced for linearizing power amplifiers(PAs)in long term evolution(LTE)/5G systems.Different from the conventional direct learning and indirect learning structure,the proposed DPD suggests a two-step method to identify the predistortion.Firstly,a negative feedback based iteration is used to estimate the optimal DPD signal.Then the corresponding DPD parameters are extracted by forward modeling with the input signal and optimal DPD signal.The iteration can be applied to both single-band and dual-band PAs,which will achieve superior linear performance than the conventional direct learning DPD while having a relatively low computational complexity.The measurement is carried out on a broadband Doherty PA(DPA)with a 200 MHz bandwidth LTE signal at 2.1 GHz,and on a 5G DPA with two 10 MHz LTE signals at 3.4/3.6 GHz for validation in dual-band scenarios.

Low Noise Amplifier Design for Digital Television Applications

The DVB-T (Digital Video Broadcasting—Terrestrial) standard is being deployed in many parts of the world for digital broadcasting services, providing a variety of features extending the capabilities of the older analog ones. In this paper, a two-stage low noise amplifier (LNA) is designed for use with the DVB-T standard. The design is employed based on microstrip. The microwave design meets all the specifications required, achieving input and output return loss below ?10 dB, high gain of 35 dB and high linearity. Low noise figure of 1.3 dB is achieved with the use of pHEMT transistor technology.

Networking Intelligent Pressure Sensor Using Digital Lock-in Amplification Technology

Introducing a System-on-Chip （SoC） microcontroller （C8051F350） into a ceramic pressure sensor has resulted in the design of a intelligent sensor. An improved algorithm for digital phassensitive detection is used to perform lock-in amplification of the sensor signal. The compensation for the sensor error is realized by the detection of the sensor＇s supply voltage and working temperature. The system also has the function of short/open circuit fault detection and can ommamicate with other digital equipment through an RS-485 communication interface. In the design, full utilization of the SoC microcontroller＇ s internal resource results in the simple hardware structure. Experimental results show that the error of the sensor is less than 0.5% at range ratio 1 ： 10. Employing the microcontroller and using lock-in amplification algorithm are an effective method for achieving an intelligent sensor of slowly-varying physical quantities, thereby improving the measuring accuracy and performance.

Robust Digital Control of a Broadband PWM Power Amplifier

Lately, it is required that the bandwidth of PWM （pulse width modulation） power amplifier is extended. For example, it is in application of the testing power supply of a low frequency immunity examination, or a class-D amplifier. In this paper, the authors show that the bandwidth of PWM power amplifier can be controller. This controller is implemented on a DSP （digital can be made wider with this controller. extended by using an approximate 2DOF （2-degree-of-freedom） digital signal processor）. It is demonstrated from experiments that the bandwidth

Capacitance Sensing and Software-Realized Lock-in Amplifier for the Electromagnetically Levitated Micro Gyroscope

In the novel prototype of micro-gyroscope structure,the new configured capacitance sensing scheme for the micro gyroscope was analyzed and the virtual instrument based detection scheme was implemented.The digital lock-in amplifier was employed in the capacitance detection to restrain the noise interference.The capacitance analysis shows that 1 fF capacitance variation corresponds to 0.1 degree of the turn angle.The differential capacitance bridge and the charge integral amplifier were used as the front signal input interface.In the implementation of digital lock-in amplifier,a new routine which warranted the exactly matching of the reference phase to signal phase was proposed.The result of the experiment shows that digital lock-in amplifier can greatly eliminate the noise in the output signal.The non linearity of the turn angle output is 2.3% and the minimum resolution of turn angle is 0.04 degrees.The application of the software demodulation in the signal detection of micro-electro-mechanical-system(MEMS)device is a new attempt,and it shows the prospective for a high-performance application.

A virtual lock-in amplifier,spectrum analyzer,impedance meter and semiconductor analyzer implemented on an SR7265 hardware target

Lock-in amplifiers are used to detect and measure very small alternating current(AC)signals down to the range of nVs.Accurate measurements can be made even when the small signals are buried by noise thousands of times larger.With the digital signal processing(DSP)technology involved in modern instrumentation,a lock-in amplifier is more versatile in sensing and recovering small signals.Combining the virtual instrumentation technology,we reorganize the functional blocks of a programmable lock-in amplifier and build it as a virtual spectrum analyzer,virtual impedance meter,virtual network analyzer,virtual semiconductor parameter analyzer,signal generator,etc.A 4 layer model is used to implement these virtual instruments.The same virtual instrument can also be implemented on a general purpose FPGA developing board.

Design of Si-bipolar Monolithic Main Amplifier IC for Optical Fiber Receivers

A broadband amplifier with transadmittance and transimpedance stages is designed and two types of improved AGC amplifiers are developed on the base of theory study. Making use of the basic amplifier cells, a main amplifier IC for optical-fiber receivers is deliberated. By computer simulating the performances of the designed main amplifier meet the necessity of high gain and wide dynamic range . They are maximum voltage gain of 42 dB, the bandwidth of 730 MHz,the input signal( V p-p )range from 5 mV to 1 V,the output amplitude about 1 V, the dynamic range of 46 dB. The designed circuit containing no inductance and large capacitance will be convenient for realizing integration. A monolithic integrated design of 622 Mb/s main amplifier is completed.

A Strong Anti-Jamming Algorithm Based on FPGA for Estimating Loop Delay in Digital Predistortion System

At present what are the key points focused in the research of loop-delay estimation for the digital predistorter in the radio frequency （RF） power amplifier system is reducing its complexity of engineering realization and improving anti-jamming ability and computational speed. Besides, opening up its application scope should be contained. For these targets, a novel method including integer loop delay estimation and fractional part is proposed. The integer part applies amplitude-difference summation function and the fractional one adopts the method of finite impulse response （FIR） linear interpolation. The algorithm finds wide applications. What is more, strong anti-jamming ability and low complexity are also its merits. Simulation results support the above opinion. Digital predistortion （DPD） system based on this algorithm achieves good performance.

The Beijing network of digital geomagnetic pulsation observatories

We present herein an introduction to the Beijing network of digital geomagnetic pulsation observatories, and describe its essential features, and important roles in earthquake prediction studies and other geomagnetic investigations. The network provides digitalized data of geomagnetic events, such as magnetic storms, magnetic disturbances, geomagnetic daily variations, and geomagnetic pulsations. The digitalized data, convenient for processing and analysis, contain very rich information because of high accuracy and wide dynamic range of the instruments.

FPGA Implementation of a Power Amplifier Linearizer for an ETSI-SDR OFDM Transmitter

Most satellite digital radio （SDR） systems use orthogonal frequency-division multiplexing （OFDM） transmission, which means that variable envelope signals are distorted by the RF power amplifier （PA）. It is customary to back off the input power to the PA to avoid the PA nonlinear region of operation. In this way, linearity can be achieved at the cost of power efficiency. Another attractive option is to use a linearizer, which compensates for the nonlinear effects of the PA. In this paper, an OFDM transmitter conforming to European Telecommunications Standard Institute SDR Technical Specifications 2007-2008 was designed and implemented on a low-cost field-programmable gate array （FPGA） platform. A weakly nonlinear PA, operating in the L-band SDR frequency, was used for signal transmission. An adaptive linearizer was designed and implemented on the same FPGA device using digital predistortion to correct the undesired effects of the PA on the transmitted signal. Test results show that spectral distortion can be suppressed between 6-9 dB using the designed linearizer when the PA is driven close to its saturation region.

Fault Waveform Regenerator and Its Digital Closed-Loop Modification Technique

In order to provide a novel and more effective alternative to the commonly used relay protection testing device that outputs only the sinusoidal testing signals, the concept of fault waveform regenerator is proposed in this paper, together with its hardware structure and software flow chart. Fault waveform regenerator mainly depends on its power amplifiers (PAs) to regenerate the fault waveforms recorded by digital fault recorder (DFR). To counteract the PA’s inherent nonlinear distortions, a digital closed-loop modification technique that is different from the predistortion technique is conceived. And the experimental results verify the effectiveness of the fault waveform regenerator based on the digital closed-loop modification technique.

NONLINEAR CHARACTERIZATION OF CONCURRENT DUAL-BAND RF POWER AMPLIFIERS

In this paper, the synchronous concurrent dual-band RF signal is used to drive the RF Power Amplifier (PA). The nonlinear characterization of a concurrent dual-band RF PA is discussed while two band signals in the dual-band are modulated by CDMA2000 and WCDMA signals. When the two band signals in the dual-band of the PA are modulated with the same signals, it is found that the nonlinearity of the PA can be expressed by any of the two corresponding baseband data. On the other hand, when the two band signals in the dual-band of the PA are modulated with two different signals, the PA nonlinearity cannot be characterized by any of the two corresponding baseband data. In this case, its nonlinearity has to be denoted by a composite signals consisting of the two baseband signals. Consequently, the requirements for the speed of the A/D converter can be largely reduced. The experimental results with CDMA2000 and WCDMA signals demonstrate the speed of the A/D converter required is only 30 M Sample Per Second (SaPS), but it will be at least 70 M SaPS for the conventional method.

A Parallel Amplifier Structure for Increasing Dynamic Range of EW Receivers

In Electronic Warfare （EW） receivers, the desired Dynamic Range （DR） often far exceeds the dynamic range attainable with available Analog-to-Digital Converter （ADC） technology. ADC is the key bottleneck in achieving the needed dynamic range. In this paper, an approach for improving the effective DR by utiliTing multiple amplifiers is presented. The amplifiers, arranged in parallel channels with different gains, can increase the dynamic range greatly.

低峰均比M-APSK波形的功率放大器数字预失真仿真分析

针对新一代散射通信对通信距离、传输速率、调制波形的更高需求,对散射通信大功率放大器提出了更高要求。利用星座图分析了M-APSK的峰均比,分析了功率放大器的Volterra级数与记忆多项式两种非线性模型,设计了自适应数字预失真技术的仿真方案,并进行了M-APSK波形下的功率放大器数字预失真仿真。结果表明,功率放大器通过数字预失真可以显著改善M-APSK调制波形信号质量。

基于数字放大器的电容数字转换器

为了实现较高的电容检测范围,传统的采用SAR ADC的开关电容(Switched capacitor,SC)的电容数字转换器(Capacitance to digital converter,CDC)使用高压供电提高输出摆幅,而其为了保证噪声性能又采用大电流驱动,所以显著增加了系统功耗。为了解决以上问题,提出了一种基于数字放大器的电容数字转换器,将CDAC阵列作为模拟输出承担高压。仅对CDAC阵列与传感电容采用高压(5 V)驱动,而其余部分仍采用低压(1 V)供电,使得CDC在达到高动态范围与高灵敏度的同时保持低功耗、低噪声。此外,针对噪声的优化,本文一方面通过在数字放大器内加入积分环路实现SAR ADC的一阶噪声整形,降低了系统的量化噪声,提高了CDC的有效位数;另一方面通过引入有源噪声抵消(Active noise cancellation technology,ANC)技术,降低了系统的混叠噪声,提高了系统的信噪比。

一种具有1~128倍可变增益放大器的低功耗Sigma⁃Delta ADC

为满足传感器应用的低功耗需求,设计并实现了一种低功耗Sigma⁃Delta模数转换器(ADC)芯片。该ADC采用一阶全差分开关电容Sigma⁃Delta调制器,且集成了可编程增益放大器(PGA)和Bandgap;使用1.5 bit量化结构,相较于1 bit量化结构减小了3 dB的量化误差;使用优化的反馈电路,减小了电容失配引入的误差;PGA采用轨到轨的运放电路拓扑,增大了整个芯片的电压适应范围。基于180 nm CMOS工艺对该ADC进行了设计和流片。测试结果表明:该Sigma⁃Delta ADC在采样频率512 kHz、过采样率(OSR)为256时,峰值信噪谐波失真比(SNDR)和有效位数(ENOB)分别为75.29 dB和12.21 bit,芯片功耗仅为0.92 mW。芯片能在2.3~5.5 V宽电源电压范围内正常工作,可实现最大128 V/V的增益。适用于小型传感器的信号测量应用,可以满足小型传感器低功耗、高精度的需求。

数字直驱中波发射机多功能功放测试平台的设计与实现

随着使用年限的累积,中波广播发射机的故障率逐渐上升,功放模块等关键部件的损坏变得更加频繁。原厂备件价格高昂且采购周期较长,对发射机的运维带来显著负面影响。本文设计开发了具有自主知识产权的新型数字直驱中波发射机功放测试平台,为功放模块维修提供了完备的测试环境,降低了对于原厂采购的依赖,为安全播出提供了有力保障,具有一定的示范作用。