An open-ended and multifunctional double-channel signal generator, which based on a 32 bits monolithic integrated microcomputer, highly integrated device and LCD, is introduced in this paper. The instrument is compose...An open-ended and multifunctional double-channel signal generator, which based on a 32 bits monolithic integrated microcomputer, highly integrated device and LCD, is introduced in this paper. The instrument is composed of micro-computer STM32F103RD and some integrated chips (IC), which includes programmable waveform generators-AD9833 with highly frequency and phase precision. As a result, this signal generator may output not only double channels accurate sine, square or triangle waveforms with digital-controlled frequency and phase at the same time, but also many kinds of physiological signals that can be modified by USB connection with well open property. Therefore, it is convenient to measure and teach about hearing, research and study on frequency characteristic of human ear and impedance characteristic of human body in medical science. In addition, it is also very easy in experiment and research of college and medical physics for using double channels sine signal to show synthesis of two simple harmonic vibrations under different frequency, phase difference and direction, such as beat pattern and Lissajous figures. Thus it has many merits, such as the small volume, stable property, simple operation, visual display and so on. Consequently, it can be widely used in researching, teaching, debugging and maintaining.展开更多
A memory compress algorithm for 12\|bit Arbitrary Waveform Generator (AWG) is presented and optimized. It can compress waveform memory for a sinusoid to 16×13bits with a Spurious Free Dynamic Range (SFDR) 90.7dBc...A memory compress algorithm for 12\|bit Arbitrary Waveform Generator (AWG) is presented and optimized. It can compress waveform memory for a sinusoid to 16×13bits with a Spurious Free Dynamic Range (SFDR) 90.7dBc (1/1890 of uncompressed memory at the same SFDR) and to 8×12bits with a SFDR 79dBc. Its hardware cost is six adders and two multipliers. Exploiting this memory compress technique makes it possible to build a high performance AWG on a chip.展开更多
国防科技大学自主研制的高性能加速器采用中央处理器(CPU)+通用数字信号处理器(GPDSP)的片上异构融合架构,使用超长指令集(VLIW)+单指令多数据流(SIMD)的向量化结构的GPDSP是峰值性能主要支撑的加速核。主流编译器在密集的数据计算指令...国防科技大学自主研制的高性能加速器采用中央处理器(CPU)+通用数字信号处理器(GPDSP)的片上异构融合架构,使用超长指令集(VLIW)+单指令多数据流(SIMD)的向量化结构的GPDSP是峰值性能主要支撑的加速核。主流编译器在密集的数据计算指令排布、为指令静态分配硬件执行单元、GPDSP特有的向量指令等方面不能很好地支持高性能加速器。基于低级虚拟器(LLVM)编译框架,在前寄存器分配调度阶段,结合峰值寄存器压力感知方法(PERP)、蚁群优化(ACO)算法与GPDSP结构特点,优化代价模型,设计支持寄存器压力感知的指令调度模块;在后寄存器分配阶段提出支持静态功能单元分配的指令调度策略,通过冲突检测机制保证功能单元分配的正确性,为指令并行执行提供软件基础;在后端封装一系列丰富且规整的向量指令接口,实现对GPDSP向量指令的支持。实验结果表明,所提出的LLVM编译架构优化方法从功能和性能上实现了对GPDSP的良好支撑,GCC testsuite测试整体性能平均加速比为4.539,SPEC CPU 2017浮点测试整体性能平均加速比为4.49,SPEC CPU 2017整型测试整体性能平均加速比为3.24,使用向量接口的向量程序实现了平均97.1%的性能提升率。展开更多
Digital PreDistortion(DPD)is a very useful method to improve the linearity of Power Amplifiers(PAs)for LTE and upcoming 5 G networks.As the spectrum resources are becoming more and more crowded,and the communications ...Digital PreDistortion(DPD)is a very useful method to improve the linearity of Power Amplifiers(PAs)for LTE and upcoming 5 G networks.As the spectrum resources are becoming more and more crowded,and the communications bandwidth are broader,the ACPR(Adjacent Channel Leakage Ratio)is very important to communication systems.DPD is one of the useful means for PA to reduce ACPR.This article demonstrates what DPD is and how DPD is achieved,the measurement of the Digital Distortion of a PA using a vector generator and vector analyzer,and the measurement results has been discussed.展开更多
The transistor voltage regulators have been widely adopted in the brushless AC generators in aircraft. This paper researches the digital voltage regulator. The paper presents the hardware platform of the digital volta...The transistor voltage regulators have been widely adopted in the brushless AC generators in aircraft. This paper researches the digital voltage regulator. The paper presents the hardware platform of the digital voltage regulator, which is based on a DSP chip — TMS320C32. A novel fuzzy filter control structure is developed from normal fuzzy control strategy. And the fuzzy filter control algorithm is adopted in the hardware platform successfully. The computer simulation has been conducted. Some control parameters have been obtained through the simulation. The same parameters have been applied in the digital regulation experiments on a brushless AC generator. In the experiment, the digital voltage regulator results in good responses. From the experiment results, it can be seen that the new control algorithm is efficient for the digital voltage regulator.展开更多
数字信号处理器(digital signal processor,DSP)通常采用超长指令字(very long instruction word,VLIW)和单指令多数据(single instruction multiple data,SIMD)的架构来提升处理器整体计算性能,从而适用于高性能计算、图像处理、嵌入...数字信号处理器(digital signal processor,DSP)通常采用超长指令字(very long instruction word,VLIW)和单指令多数据(single instruction multiple data,SIMD)的架构来提升处理器整体计算性能,从而适用于高性能计算、图像处理、嵌入式系统等各个领域.飞腾迈创数字处理器(FT-Matrix)作为国防科技大学自主研制的高性能通用数字信号处理器,其极致计算性能的体现依赖于对VLIW与SIMD架构特点的充分挖掘.不止是飞腾迈创系列,绝大多数处理器上高度优化的内核代码或核心库函数都依赖于底层汇编级工具或手工开发.然而,手工编写内核算子的开发方法总是需要大量的时间和人力开销来充分释放硬件的性能潜力.尤其是VLIW+SIMD的处理器,专家级汇编开发的难度更为突出.针对这些问题,提出一种面向飞腾迈创数字处理器的高性能的内核代码自动生成框架(automatic kernel code-generation framework on FT-Matrix),将飞腾迈创处理器的架构特性引入到多层次的内核代码优化方法中.该框架包括3层优化组件:自适应循环分块、标向量协同的自动向量化和细粒度的指令级优化.该框架可以根据硬件的内存层次结构和内核的数据布局自动搜索最优循环分块参数,并进一步引入标量-向量单元协同的自动向量化指令选择与数据排布,以提高内核代码执行时的数据复用和并行性.此外,该框架提供了类汇编的中间表示,以应用各种指令级优化来探索更多指令级并行性(ILP)的优化空间,同时也为其他硬件平台提供了后端快速接入和自适应代码生成的模块,以实现高效内核代码开发的敏捷设计.实验表明,该框架生成的内核基准测试代码的平均性能是目标-数字信号处理器(DSP)--的手工函数库的3.25倍,是使用普通向量C语言编写的内核代码的20.62倍.展开更多
文摘An open-ended and multifunctional double-channel signal generator, which based on a 32 bits monolithic integrated microcomputer, highly integrated device and LCD, is introduced in this paper. The instrument is composed of micro-computer STM32F103RD and some integrated chips (IC), which includes programmable waveform generators-AD9833 with highly frequency and phase precision. As a result, this signal generator may output not only double channels accurate sine, square or triangle waveforms with digital-controlled frequency and phase at the same time, but also many kinds of physiological signals that can be modified by USB connection with well open property. Therefore, it is convenient to measure and teach about hearing, research and study on frequency characteristic of human ear and impedance characteristic of human body in medical science. In addition, it is also very easy in experiment and research of college and medical physics for using double channels sine signal to show synthesis of two simple harmonic vibrations under different frequency, phase difference and direction, such as beat pattern and Lissajous figures. Thus it has many merits, such as the small volume, stable property, simple operation, visual display and so on. Consequently, it can be widely used in researching, teaching, debugging and maintaining.
文摘A memory compress algorithm for 12\|bit Arbitrary Waveform Generator (AWG) is presented and optimized. It can compress waveform memory for a sinusoid to 16×13bits with a Spurious Free Dynamic Range (SFDR) 90.7dBc (1/1890 of uncompressed memory at the same SFDR) and to 8×12bits with a SFDR 79dBc. Its hardware cost is six adders and two multipliers. Exploiting this memory compress technique makes it possible to build a high performance AWG on a chip.
文摘国防科技大学自主研制的高性能加速器采用中央处理器(CPU)+通用数字信号处理器(GPDSP)的片上异构融合架构,使用超长指令集(VLIW)+单指令多数据流(SIMD)的向量化结构的GPDSP是峰值性能主要支撑的加速核。主流编译器在密集的数据计算指令排布、为指令静态分配硬件执行单元、GPDSP特有的向量指令等方面不能很好地支持高性能加速器。基于低级虚拟器(LLVM)编译框架,在前寄存器分配调度阶段,结合峰值寄存器压力感知方法(PERP)、蚁群优化(ACO)算法与GPDSP结构特点,优化代价模型,设计支持寄存器压力感知的指令调度模块;在后寄存器分配阶段提出支持静态功能单元分配的指令调度策略,通过冲突检测机制保证功能单元分配的正确性,为指令并行执行提供软件基础;在后端封装一系列丰富且规整的向量指令接口,实现对GPDSP向量指令的支持。实验结果表明,所提出的LLVM编译架构优化方法从功能和性能上实现了对GPDSP的良好支撑,GCC testsuite测试整体性能平均加速比为4.539,SPEC CPU 2017浮点测试整体性能平均加速比为4.49,SPEC CPU 2017整型测试整体性能平均加速比为3.24,使用向量接口的向量程序实现了平均97.1%的性能提升率。
基金supported by Shenzhen Strategic Emerging Industry Development Fund Project——Public service platform for 5G key components testing(20170921165224440)
文摘Digital PreDistortion(DPD)is a very useful method to improve the linearity of Power Amplifiers(PAs)for LTE and upcoming 5 G networks.As the spectrum resources are becoming more and more crowded,and the communications bandwidth are broader,the ACPR(Adjacent Channel Leakage Ratio)is very important to communication systems.DPD is one of the useful means for PA to reduce ACPR.This article demonstrates what DPD is and how DPD is achieved,the measurement of the Digital Distortion of a PA using a vector generator and vector analyzer,and the measurement results has been discussed.
基金Pre-research subject of the 9-th 5 year plan for National Defenc
文摘The transistor voltage regulators have been widely adopted in the brushless AC generators in aircraft. This paper researches the digital voltage regulator. The paper presents the hardware platform of the digital voltage regulator, which is based on a DSP chip — TMS320C32. A novel fuzzy filter control structure is developed from normal fuzzy control strategy. And the fuzzy filter control algorithm is adopted in the hardware platform successfully. The computer simulation has been conducted. Some control parameters have been obtained through the simulation. The same parameters have been applied in the digital regulation experiments on a brushless AC generator. In the experiment, the digital voltage regulator results in good responses. From the experiment results, it can be seen that the new control algorithm is efficient for the digital voltage regulator.
文摘数字信号处理器(digital signal processor,DSP)通常采用超长指令字(very long instruction word,VLIW)和单指令多数据(single instruction multiple data,SIMD)的架构来提升处理器整体计算性能,从而适用于高性能计算、图像处理、嵌入式系统等各个领域.飞腾迈创数字处理器(FT-Matrix)作为国防科技大学自主研制的高性能通用数字信号处理器,其极致计算性能的体现依赖于对VLIW与SIMD架构特点的充分挖掘.不止是飞腾迈创系列,绝大多数处理器上高度优化的内核代码或核心库函数都依赖于底层汇编级工具或手工开发.然而,手工编写内核算子的开发方法总是需要大量的时间和人力开销来充分释放硬件的性能潜力.尤其是VLIW+SIMD的处理器,专家级汇编开发的难度更为突出.针对这些问题,提出一种面向飞腾迈创数字处理器的高性能的内核代码自动生成框架(automatic kernel code-generation framework on FT-Matrix),将飞腾迈创处理器的架构特性引入到多层次的内核代码优化方法中.该框架包括3层优化组件:自适应循环分块、标向量协同的自动向量化和细粒度的指令级优化.该框架可以根据硬件的内存层次结构和内核的数据布局自动搜索最优循环分块参数,并进一步引入标量-向量单元协同的自动向量化指令选择与数据排布,以提高内核代码执行时的数据复用和并行性.此外,该框架提供了类汇编的中间表示,以应用各种指令级优化来探索更多指令级并行性(ILP)的优化空间,同时也为其他硬件平台提供了后端快速接入和自适应代码生成的模块,以实现高效内核代码开发的敏捷设计.实验表明,该框架生成的内核基准测试代码的平均性能是目标-数字信号处理器(DSP)--的手工函数库的3.25倍,是使用普通向量C语言编写的内核代码的20.62倍.