Symbol detection based on Voronoi surfaces with emphasis on superposition modulation

A challenging task when applying high-order digital modulation schemes is the complexity of the detector. Particularly, the complexity of the optimal a posteriori probability （APP） detector increases exponentially with respect to the number of bits per data symbol. This statement is also true for the Max-Log-APP detector, which is a common simplification of the APP detector. Thus it is important to design new detection algorithms which combine a sufficient performance with low complexity. In this contribution, a detection algorithm for two- dimensional digital modulation schemes which cannot be split-up into real and imaginary parts （like phase shift keying and phase-shifted snperposition modulation （PSM）） is proposed with emphasis on PSM with equal power allocation. This algorithm exploits the relationship between Max-Log-APP detection and a Voronoi diagram to determine planar surfaces of the soft outputs over the entire range of detector input values. As opposed to state-of-the-art detectors based on Voronoi surfaces, a priori information is taken into account, enabling iterative processing. Since the algorithm achieves Max-Log-APP performance, even in the presence of a priori information, this implies a great potential for complexity reduction compared to the classical APP detection.

Micro EEG/ECG signal's chopper-stabilization amplifying chip for novel drycontact electrode

Facing the body＇s EEG（electroencephalograph, 0.5–100 Hz, 5–100 μV） and ECG＇s（electrocardiogram,〈 100 Hz, 0.01–5 mV） micro signal detection requirement, this paper develops a pervasive application micro signal detection ASIC chip with the chopping modulation/demodulation method. The chopper-stabilization circuit with the RRL（ripple reduction loop） circuit is to suppress the ripple voltage, which locates at the single-stage amplifier＇s outputting terminal. The single-stage chopping core＇s noise has been suppressed too, and it is beneficial for suppressing noises of post-circuit. The chopping core circuit uses the PFB（positive feedback loop） to increase the inputting resistance, and the NFB（negative feedback loop） to stabilize the 40 dB intermediate frequency gain. The cascaded switch-capacitor sample/hold circuit has been used for deleting spike noises caused by non-ideal MOS switches, and the VGA/BPF（voltage gain amplifier/band pass filter） circuit is used to tune the chopper system＇s gain/bandwidth digitally. Assisted with the designed novel dry-electrode, the real test result of the chopping amplifying circuit gives some critical parameters： 8.1 μW/channel, 0.8 μVrms（@band-widthD100 Hz）, 4216–11220 times digitally tuning gain range, etc. The data capture system uses the NI CO＇s data capturing DAQmx interface,and the captured micro EEG/ECG＇s waves are real-time displayed with the PC-Labview. The proposed chopper system is a unified EEG/ECG signal＇s detection instrument and has a critical real application value.