This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,th...This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter（DAC） mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications.展开更多
Video signal processing needs high signal-to-noise ratio （SNR） in high-speed time delay and integration charge coupled devices （TDICCD）. To solve this problem, this article first analyzes the characteristics of th...Video signal processing needs high signal-to-noise ratio （SNR） in high-speed time delay and integration charge coupled devices （TDICCD）. To solve this problem, this article first analyzes the characteristics of the output video signal of a new type of high-speed TDICCD and its operation principle. Then it studies the correlation double sample （CDS） method of reducing noise. Following that a synthesized processing method is proposed, including correlation double sample, programmable gain control, line calibration and digital offset control, etc. Among the methods, XRD98L59 is a video signal processor for the charge coupled device （CCD）. Application of this processor to one kind of high-speed TDICCD with eight output ports achieves perfect video images. The experiment result indicates that the SNR of the images reaches about 50 dB. The video signal processing for high-speed multi-channel TDICCD is implemented, which meets the required project index.展开更多
文摘This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter（DAC） mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications.
文摘Video signal processing needs high signal-to-noise ratio （SNR） in high-speed time delay and integration charge coupled devices （TDICCD）. To solve this problem, this article first analyzes the characteristics of the output video signal of a new type of high-speed TDICCD and its operation principle. Then it studies the correlation double sample （CDS） method of reducing noise. Following that a synthesized processing method is proposed, including correlation double sample, programmable gain control, line calibration and digital offset control, etc. Among the methods, XRD98L59 is a video signal processor for the charge coupled device （CCD）. Application of this processor to one kind of high-speed TDICCD with eight output ports achieves perfect video images. The experiment result indicates that the SNR of the images reaches about 50 dB. The video signal processing for high-speed multi-channel TDICCD is implemented, which meets the required project index.
