Hybrid Simulation of ±500 kV HVDC Power Transmission Project Based on Advanced Digital Power System Simulator

In order to effectively imitate the dynamic operation characteristics of the HVDC （high voltage direct current） power transmission system at a real ±500kV HVDC transmission project, the electromechanical-electromagnetic transient hybrid simulation was carried out based on advanced digital power system simulator （ADPSS）. In the simulation analysis, the built hybrid model＇s dynamic response outputs under three different fault conditions are considered, and by comparing with the selected fault recording waveforms, the validities of the simulation waveforms are estimated qualitatively. It can be ascertained that the hybrid simulation model has the ability to describe the HVDC system＇s dynamic change trends well under some special fault conditions.

Research and realization of PWM drive control digitalization for the full digital welding power supply

Pulse width modulation （ PWM） drive control digitalization is the key for the full digital invert power supply. New ideas are proposed, which are based on field programmable gate array （ FPGA ）. First, digital PWM principles are discussed. The primary and secondary current characteristics are analyzed when the transformer is in both normal and magnetic bias conditions. Second, two digitalization methods are put forward after the research on PWM adjustment principles, which are based on the primary current feedback. Though the two methods could restrain magnetic bias, their realization is difficult. A new method is researched on double close-loops to overcome the above shortcomings, which uses the secondary current as the feedback signal and the primary current as the protection signal. Finally, the secondary current control made is discussed and realized. Welding experimental results show that the method has strong flexibility and adaptability, which can be used to realize the full digital welding power supply.

A Low Power Non-Volatile LR-WPAN Baseband Processor with Wake-Up Identification Receiver

The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.

Research on the application of digital power supply based on domestic FPGA

Purpose The digital controller for the accelerator magnet power supply typically employs a field-programmable gate array(FPGA)as the signal processing chip for executing digital processing of closed-loop control.Currently,FPGA chips are predominantly utilized in Intel or Xilinx products.To address the“key areas and stranglehold”issue pertaining to FPGA chips in accelerator power supply,we have devised a digital power supply prototype using a domestic FPGA chip and validated its feasibility in the upgrade project’s magnet power supply digital transformation plan for the Beijing Electron Positron Collider(BEPCII).Method A domestic FPGA chip from the Seal5000 SA5Z-30-D1 series by Xi’an ZhiDuoJing Microelectronics Co.serves as the core component for the design of a digital corrector magnet power supply to replace the existing analog controlled corrector power supply at BEPCII.The power supply’s digital control of the closed loop is achieved through the use of a hardware description language,and the digital controller hardware is constructed based on the original power supply power topology.Results and conclusions After conducting experiments and tests on the power supply prototype,we have successfully met the current operational requirements of the BEPCII corrector power supply,thus confirming the feasibility of utilizing domestic FPGA for digital application on accelerator power supply.

CMOS vision sensor with fully digital image process integrated into low power 1/8-inch chip

A digital still camera image processing system on a chip, different from the video camera system, is pre- sented for mobile phone to reduce the power consumption and size. A new color interpolation algorithm is proposed to enhance the image quality. The system can also process fixed patten noise （FPN） reduction, color correction, gamma correction, RGB/YUV space transfer, etc. The chip is controlled by sensor regis- ters by inter-integrated circuit （I2C） interface. The voltage for both the front-end analog and the pad cir- cuits is 2.8 V, and the volatge for the image signal processing is 1.8 V. The chip running under the external 13.5-MHz clock has a video data rate of 30 frames/s and the measured power dissipation is about 75 roW.

Digital Power Electronics

High frequency switching circuits can effectively increase the power density, efficiency, reliability and flexibility, and reduce power losses and equipment cost. Consequently, high-frequency switching circuits have been paid much attention in recent decades. These performances are thoroughly different from traditional analogue control systems. Till now there is no suitable theory to describe the characteristics of the switching circuits and systems. A new theory entitled 'Digital Power Electronics' presents the clue of switching operation (switching period T=1/f,f is the switching frequency) and the pumping-filtering process,resonant operation and softswitching methodology,and researched the rules of power switching circuits and systems. The new parameters Energy Factor (EF), Pumping Energy (PE), Stored Energy (SE), Capacitor- Inductor stored energy Ratio (CIR) and time constants r and r d. Using these new parameters,ZOH/FOH/SOH and the z-transform can well describe the characteristics of power switching circuits and systems.

Digital Engine Powers New Economy

Internet 已成为推动世界经济的强大动力。在美国Internet经济的总额1996年为155亿美元,1997年增加到390亿美元,预计到2001年将猛增至3500亿美元。所以本文作者认为Internet正在推动美国新经济(new economy)时代的到来,并指出与美国的商业部门相比较,美国的政府和教育部门已在Internet经济中落后。尤其是教育。如在过去5年中美国有博士学位的工程师中的1/4来自国外。

A digitally controlled PWM/PSM dual-mode DC/DC converter

A digitally controlled pulse width modulation/pulse skip modulation （PWM/PSM） dual-mode buck DC/DC converter is proposed. Its operation mode can be automatically chosen as continuous conduction mode （CCM） or discontinuous conduction mode （DCM）. The converter works in PSM at DCM and in 2 MHz PWM at CCM. Switching loss is reduced at a light load by skipping cycles. Thus high conversion efficiency is realized in a wide load current. The implementations of PWM control blocks, such as the ADC, the digital pulse width modulator （DPWM） and the loop compensator, and PSM control blocks are described in detail. The parameters of the loop compensator can be programmed for different external component values and switching frequencies, which is much more flexible than its analog rivals. The chip is manufactured in 0.13 μm CMOS technology and the chip area is 1.21 mm^2. Experimental results show that the conversion efficiency is high, being 90% at 200 mA and 67% at 20 mA. Meanwhile, the measured load step response shows that the proposed dual-mode converter has good stability.

Low sampling rate technique based frequency-domain random demodulation for broadband digital predistortion

This paper proposes a combination technique of the frequency-domain random demodulation（FRD） and the broadband digital predistorter（DPD）. This technique can linearize the power amplifiers（PAs） at a low sampling rate in the feedback loop. Based on the theory of compressed sensing（CS）, the FRD method preprocesses the original signal using the frequency domain sampling signal with different stages through multiple parallel channels. Then the FRD method is applied to the broadband DPD system to restrict the sampling process in the feedback loop. The proposed technique is assessed using a 30 W Class-F wideband PA driven by a 20 MHz orthogonal frequency division multiplexing（OFDM） signal, and a 40 W Ga N Doherty PA driven by a 40 MHz 4-carrier long-term evolution（LTE） signal. The simulation and experimental results show that good linearization performance can be achieved at a lower sampling rate with about- 24 d Bc adjacent channel power ratio（ACPR） improvement by applying the proposed combination technique FRD-DPD. Furthermore, the performance of normalized mean square error（NMSE） and error vector magnitude（EVM） also has been much improved compared with the conventional technique.

A 1.2-V,84-dB∑△ADM in 0.18-μm digital CMOS technology

A low power and low voltage∑△analog-to-digital modulator is realized with digital CMOS technology, which is due to full compensated depletion mode capacitors.Compared with mixed signal technology,this type of modulator is more compatible for pure digital applications.A pseudo-two-stage class-AB OTA is used in switchedcapacitor integrators for low voltage and low power.The modulator is realized in standard SMIC 0.18μm 1P6M digital CMOS technology.Measured results show that with 1.2 V supply voltage and a 6 MHz sample clock,the dynamic range of the modulator is 84 dB and the total power dissipation is 2460μW.

Scaling trends in energy recovery logic:an analytical approach

This paper presents an analytical model to study the scaling trends in energy recovery logic.The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage,device threshold voltage and gate oxide thickness.The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale.This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.