Thelinearityofcurrent-steeringdigital-to-analogconverters（DACs）atlowsignalfrequenciesismainly limited by matching properties of current sources, so large-size current source arrays are widely used for better matchin...Thelinearityofcurrent-steeringdigital-to-analogconverters（DACs）atlowsignalfrequenciesismainly limited by matching properties of current sources, so large-size current source arrays are widely used for better matching. This, however, results in large gradient errors and parasitic capacitance, which degrade the spurious free dynamic range（SFDR） for high-frequency signals. To overcome this problem, calibration is an effective method.In this paper, a digital background calibration technique for current-steering DACs is presented and verified by a 14-bit DAC in a 0.13 m standard CMOS process. The measured differential nonlinearity（DNL） and integral nonlinearity（INL） are 0.4 LSB and 1.2 LSB, respectively. At 500-MS/s, the SFDR is 70 dB and 50.3 dB for signals of 5.4 MHz and 224 MHz, respectively. The core area is 0.69 mm2and the power consumption is 165 mW from a mixed power supply with 1.2 V and 3.3 V.展开更多
This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC） with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog con...This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC） with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter （MDAC） while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3 × 1.6 mm^2, and consumes 205 mW at 1.8 V.展开更多
This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the...This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the sum of the first derivative of the digital output. The least-mean-square (LMS) loop is exploited to compensate the timing skew. Since the calibration scheme depends on the digital output, all timing skew sources can be calibrated and the main ADC is maintained. The proposed scheme is effective within the entire frequency range of 0 ? fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes significantly lesser power and smaller area.展开更多
This paper presents a two-mode digital calibration technique for pipelined analog-to-digital converters （ADC）.The proposed calibration eliminates the errors of residual difference voltage induced by capacitor mismat...This paper presents a two-mode digital calibration technique for pipelined analog-to-digital converters （ADC）.The proposed calibration eliminates the errors of residual difference voltage induced by capacitor mismatch of pseudorandom（PN） sequence injection capacitors at the ADC initialization,while applies digital background calibration to continuously compensate the interstage gain errors in ADC normal operation.The presented technique not only reduces the complexity of analog circuit by eliminating the implementation of PN sequence with accurate amplitude in analog domain,but also improves the performance of digital background calibration by minimizing the sensitivity of calibration accuracy to sub-ADC errors.The use of opamps with low DC gains in normal operation makes the proposed design more compatible with future nanometer CMOS technology.The prototype of a 12-bit 40-MS/s pipelined ADC with the two-mode digital calibration is implemented in 0.18-μm CMOS process.Adopting a simple telescopic opamp with a DC gain of 58-dB in the first stage,the measured SFDR and SNDR within the first Nyquist zone reach 80-dB and 66-dB,respectively.With the calibration,the maximum integral nonlinearity （INL） of the ADC reduces from 4.75-LSB to 0.65-LSB,while the ADC core consumes 82-mW at 3.3-V power supply.展开更多
This paper describes a fast digital calibration scheme for pipelined analog-to-digital converters（ADCs）. The proposed method corrects the nonlinearity caused by finite opamp gain and capacitor mismatch in multiplyin...This paper describes a fast digital calibration scheme for pipelined analog-to-digital converters（ADCs）. The proposed method corrects the nonlinearity caused by finite opamp gain and capacitor mismatch in multiplying digital-to-analog converters（MDACs）.The considered calibration technique takes the advantages of both foreground and background calibration schemes.In this combination calibration algorithm,a novel parallel background calibration with signal-shifted correlation is proposed,and its calibration cycle is very short.The details of this technique are described in the example of a 14-bit 100 Msample/s pipelined ADC.The high convergence speed of this background calibration is achieved by three means.First,a modified 1.5-bit stage is proposed in order to allow the injection of a large pseudo-random dithering without missing code.Second,before correlating the signal,it is shifted according to the input signal so that the correlation error converges quickly.Finally,the front pipeline stages are calibrated simultaneously rather than stage by stage to reduce the calibration tracking constants.Simulation results confirm that the combination calibration has a fast startup process and a short background calibration cycle of 2×2^（21） conversions.展开更多
基金Project supported by the National Natural Science Foundation of China(Nos.60976024,61306029)the National High Technology Research and Development Program of China(No.2013AA014103)
文摘Thelinearityofcurrent-steeringdigital-to-analogconverters（DACs）atlowsignalfrequenciesismainly limited by matching properties of current sources, so large-size current source arrays are widely used for better matching. This, however, results in large gradient errors and parasitic capacitance, which degrade the spurious free dynamic range（SFDR） for high-frequency signals. To overcome this problem, calibration is an effective method.In this paper, a digital background calibration technique for current-steering DACs is presented and verified by a 14-bit DAC in a 0.13 m standard CMOS process. The measured differential nonlinearity（DNL） and integral nonlinearity（INL） are 0.4 LSB and 1.2 LSB, respectively. At 500-MS/s, the SFDR is 70 dB and 50.3 dB for signals of 5.4 MHz and 224 MHz, respectively. The core area is 0.69 mm2and the power consumption is 165 mW from a mixed power supply with 1.2 V and 3.3 V.
文摘This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC） with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter （MDAC） while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3 × 1.6 mm^2, and consumes 205 mW at 1.8 V.
文摘This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the sum of the first derivative of the digital output. The least-mean-square (LMS) loop is exploited to compensate the timing skew. Since the calibration scheme depends on the digital output, all timing skew sources can be calibrated and the main ADC is maintained. The proposed scheme is effective within the entire frequency range of 0 ? fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes significantly lesser power and smaller area.
基金Project supported by the National Natural Science Foundation of China(No.90307016)the National Science and Technology Major Project of China(No.2010ZX03006-003 -01)
文摘This paper presents a two-mode digital calibration technique for pipelined analog-to-digital converters （ADC）.The proposed calibration eliminates the errors of residual difference voltage induced by capacitor mismatch of pseudorandom（PN） sequence injection capacitors at the ADC initialization,while applies digital background calibration to continuously compensate the interstage gain errors in ADC normal operation.The presented technique not only reduces the complexity of analog circuit by eliminating the implementation of PN sequence with accurate amplitude in analog domain,but also improves the performance of digital background calibration by minimizing the sensitivity of calibration accuracy to sub-ADC errors.The use of opamps with low DC gains in normal operation makes the proposed design more compatible with future nanometer CMOS technology.The prototype of a 12-bit 40-MS/s pipelined ADC with the two-mode digital calibration is implemented in 0.18-μm CMOS process.Adopting a simple telescopic opamp with a DC gain of 58-dB in the first stage,the measured SFDR and SNDR within the first Nyquist zone reach 80-dB and 66-dB,respectively.With the calibration,the maximum integral nonlinearity （INL） of the ADC reduces from 4.75-LSB to 0.65-LSB,while the ADC core consumes 82-mW at 3.3-V power supply.
基金supported by the National Key Project,China(No.2008zx010200001)
文摘This paper describes a fast digital calibration scheme for pipelined analog-to-digital converters（ADCs）. The proposed method corrects the nonlinearity caused by finite opamp gain and capacitor mismatch in multiplying digital-to-analog converters（MDACs）.The considered calibration technique takes the advantages of both foreground and background calibration schemes.In this combination calibration algorithm,a novel parallel background calibration with signal-shifted correlation is proposed,and its calibration cycle is very short.The details of this technique are described in the example of a 14-bit 100 Msample/s pipelined ADC.The high convergence speed of this background calibration is achieved by three means.First,a modified 1.5-bit stage is proposed in order to allow the injection of a large pseudo-random dithering without missing code.Second,before correlating the signal,it is shifted according to the input signal so that the correlation error converges quickly.Finally,the front pipeline stages are calibrated simultaneously rather than stage by stage to reduce the calibration tracking constants.Simulation results confirm that the combination calibration has a fast startup process and a short background calibration cycle of 2×2^（21） conversions.
