In this work,two process-variation-tolerant schemes for a current-mode sense amplifier(CSA)of RRAM were proposed:(1)hybrid read reference generator(HRRG)that tracks process-voltage-temperature(PVT)variations and solve...In this work,two process-variation-tolerant schemes for a current-mode sense amplifier(CSA)of RRAM were proposed:(1)hybrid read reference generator(HRRG)that tracks process-voltage-temperature(PVT)variations and solve the nonlinear issue of the RRAM cells;(2)a two-stage offset-cancelled current sense amplifier(TSOCC-SA)with only two capacitors achieves a double sensing margin and a high tolerance of device mismatch.The simulation results in 28 nm CMOS technology show that the HRRG can provide a read reference that tracks PVT variations and solves the nonlinear issue of the RRAM cells.The proposed TSOCC-SA can tolerate over 64% device mismatch.展开更多
The digital proportion control is introduced to improve the performance of the analog adaptive interference cancellation system （ICS）. For the high frequency parts of the signals after multiplier are not required,th...The digital proportion control is introduced to improve the performance of the analog adaptive interference cancellation system （ICS）. For the high frequency parts of the signals after multiplier are not required,the sampling frequency need not satisfy the sampling theorem for high frequency. Because the sampling,calculation and output expend time in digital control,the ideal condition,delay condition and delay-wait condition are taken into account. Through analyzing the system model with three conditions,we gain the stable conditions of the system,the optimization step factors that can make the system converge fastest and the formulas of the interference cancellation ratios （ICRs）. One step convergence can be accomplished under ideal condition,whereas the system can not converge in one step under delay condition and delay-wait condition. The calculation results show the convergence speed of delay-wait condition is slower than that of delay condition. The ICR is improved with the increase of the step factor which is in stable bound,but the convergence speed is decreased if the step factor exceeds the optimization step factor. In order to avoid that confine,the method of amending the steady state weight to improve the ICR is proposed. The analyses are in agreement with the computer simulations.展开更多
基金supported in part by the National Key R&D Program of China under Grant No.2019YFB2204800in part by the Major Scientific Research Project of Zhejiang Lab(Grant No.2019KC0AD02)+1 种基金in part by the National Natural Science Foundation of China under Grants 61904200the Strategic Priority Research Program of the Chinese Academy of Sciences under Grant No.XDB44000000。
文摘In this work,two process-variation-tolerant schemes for a current-mode sense amplifier(CSA)of RRAM were proposed:(1)hybrid read reference generator(HRRG)that tracks process-voltage-temperature(PVT)variations and solve the nonlinear issue of the RRAM cells;(2)a two-stage offset-cancelled current sense amplifier(TSOCC-SA)with only two capacitors achieves a double sensing margin and a high tolerance of device mismatch.The simulation results in 28 nm CMOS technology show that the HRRG can provide a read reference that tracks PVT variations and solves the nonlinear issue of the RRAM cells.The proposed TSOCC-SA can tolerate over 64% device mismatch.
文摘The digital proportion control is introduced to improve the performance of the analog adaptive interference cancellation system （ICS）. For the high frequency parts of the signals after multiplier are not required,the sampling frequency need not satisfy the sampling theorem for high frequency. Because the sampling,calculation and output expend time in digital control,the ideal condition,delay condition and delay-wait condition are taken into account. Through analyzing the system model with three conditions,we gain the stable conditions of the system,the optimization step factors that can make the system converge fastest and the formulas of the interference cancellation ratios （ICRs）. One step convergence can be accomplished under ideal condition,whereas the system can not converge in one step under delay condition and delay-wait condition. The calculation results show the convergence speed of delay-wait condition is slower than that of delay condition. The ICR is improved with the increase of the step factor which is in stable bound,but the convergence speed is decreased if the step factor exceeds the optimization step factor. In order to avoid that confine,the method of amending the steady state weight to improve the ICR is proposed. The analyses are in agreement with the computer simulations.
