A 5MS/s 12-Bit Successive Approximation Analog-to-Digital Converter

With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.

Mismatch Calibration Techniques in Successive Approximation Analog-to-Digital Converters

Comparator offset cancellation and capacitor self-calibration techniques used in a successive approximation analog-to-digital converter （SA-ADC） are described. The calibration circuit works in parallel with the SAADC by adding additional calibration clock cycles to pursue high accuracy and low power consumption, and the calibrated resolution can be up to 14bit. This circuit is used in a 10bit 3Msps successive approximation ADC. This chip is realized with an SMIC 0. 18μm 1.8V process and occupies 0.25mm^2 . It consumes 3. 1mW when operating at 1.8MHz. The measured SINAD is 55. 9068dB, SFDR is 64. 5767dB, and THD is - 74. 8889dB when sampling a 320kHz sine wave.

Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters: State-of-the-Art and a Design Example

This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.

Effect of ionizing radiation on dual 8-bit analog-to-digital converters (AD9058) with various dose rates and bias conditions

The radiation effects on several properties （reference voltage, digital output logic voltage, and supply current） of dual 8-bit analog-to-digital （A/D） converters （AD9058） under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity （ELDRS） under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.

A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

Novel Optical Analog-To-Digital Converter Based on Optical Time Division Multiplexing

A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.

A 71mW 8b 125MSample/s A/D Converter

A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and local generators are employed to avoid loss and overlap of clock period.The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only 71mW.It is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.

A 1.8V 10bit 100Msps Pipelined Analog to Digital Converter

A novel low-voltage,low constant-impedance switch is proposed, which not only eliminates the parasitic capacitor but also reduces the variation of switch ＂on＂ resistance. With the gain-boost technology,the operational transconductance amplifier used in this analog-to-digital converter （ADC） achieves enough DC gain and unity-gain frequency under the low voltage supply and to guarantee the performance of the sample and hold circuit （S/H） and the sub-stages. Based on these methods,a 10bit 100Msps pipelined ADC is fabricated in a 0. 18μm CMOS process and operates under a 1.8V voltage supply. The ADC achieves an SNR of 54. 2dB （input frequency of 6.26MHz） and an SNR of 49. 8dB （input frequency of 48. 96MHz） when the sampling frequency is 100MHz.

200Ms/s 177mW 8bit Folding and Interpolating CMOS A/D Converter

A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described.The circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented without resistor contributes to a small chip area.At the input stage,offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio.The 200Ms/s 8bit ADC with 177mW total power consumption at 3.3V power supply is realized in standard digital 0.18μm 3.3V CMOS technology.

Stability optimization of channel-interleaved photonic analog-to-digital converter by extracting of dual-output photonic demultiplexing

We investigate a channel-interleaved photonic analog-to-digital conversion(PADC)system’s ability to work stably over a long duration with an optimal driving voltage.The influence of optimum bias point drift of a Mach–Zehnder modulator(MZM)-based photonic switch on this system was analyzed theoretically and experimentally.The feasibility of extracting feedback signals from the PADC system was derived.A high-stability channel-interleaved PADC was constructed by extracting a feedback signal from a parallel demultiplexing module to control the MZM-based photonic switch’s driving voltage.Consequently,the amplitude mismatch between the channels was limited to within 0.3 d B over 12 hours of operation.

A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology

A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital con- verter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.

A 12-bit 250-MS/s Charge-Domain Pipelined Analog-to-Digital Converter with Feed-Forward Common-Mode Charge Control

A feed-forward Common-Mode （CM） charge control circuit for a high-speed Charge-Domain （CO） pipelined Analog-to-Digital Converter （ADC） is presented herein. This study aims at solving the problem whereby the precision of CD pipelined ADCs is restricted by the variation in input CM charge, which can compensate for CM charge errors caused by a variation in CM charge input in real time. Based on the feed-forward CM charge control circuit, a 12-bit 250-MS/s CD pipelined ADC is designed and realized using a 1P6M 0.18-μm CMOS process. The ADC achieved a Spurious Free Dynamic Range （SFDR） of 78.1 dB and a Signal-to-Noise-and-Distortion Ratio （SNDR） of 64.6 dB for a 20.1-MHz input; a SFDR of 74.9 dB and SNDR of 62.0 dB were achieved for a 239.9-MHz input at full sampling rate. The variation in signal-to-noise ratio was less than 3 dB over a 0-1.2 V input CM voltage range. The power consumption of the prototype ADC is only 85 mW at 1.8 V supply, and it occupies an active die area of 2.24 mm^2.

Switching response of dual-output Mach–Zehnder modulator in channel-interleaved photonic analog-to-digital converter

This Letter theoretically and experimentally studies the response of photonic switching in a channel-interleaved photonic analog-to-digital converter(PADC) with high sampling rate and wide input frequency range. A figure of merit(FoM) is introduced to evaluate the switching response of the PADC when a dual-output Mach–Zehnder modulator(MZM) serves as the photonic switch to parallelize the sampled pulse train into two channels. After the optimization of the FoM and utilization of the channel-mismatch compensation algorithm,the system bandwidth of PADC is expanded and the signal-to-distortion ratio is enhanced.

Wideband signal detection based on high-speed photonic analog-to-digital converter

This Letter demonstrates the effectiveness of a high-speed high-resolution photonic analog-to-digital converter （PADC） for wideband signal detection. The PADC system is seeded by a high-speed actively mode locked laser, and the sampling rate is multiplied via a time-wavelength interleaving scheme. According to the laboratory test, an X-band linear frequency modulation signal is detected and digitized by the PADC system. The channel mismatch effect in wideband signal detection is compensated via an algorithm based on a short-time Fourier transform. Consequently, the signal-to-distortion ratio （SDR） of the wideband signal detection is enhanced to the comparable SDR of the single-tone signal detection.

A Novel All-Optical Analog-to-Digital Converter

An all-optical analog-to-digital converter capable of sampling at 50GS/s is described. The ADC works in the frequency domain. The RF signal is sampled by electro-optically steerable gratings and quantized by a set of detectors with scalable apertures.

An ultra high-speed 8-bit timing interleave folding＆interpolating analog-to-digital converter with digital foreground calibration technology

A 2-Gsample/s 8-b analog-to-digital converter in 0.35μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 GSPS.Digital calibration technology is used for the offset and gain corrections of the S/H circuit,the offset correction of preamplifier,and the gain and clock phase corrections between channels.As a result of testing,the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected.

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.

Correction of timing mismatches between two channels for photonic analog-to-digital converters

This paper presents a scheme to identify and compensate the timing mismatches between two channels for tipme interleaved photonic analog-to-digital converters(TIPADCs). The impact of electro-optic sampling is removed by preprocessing firstly. Then a calibration method combining chopping processing and a Hilbert transform is proposed to identify the timing mismatches, which can be further compensated by using various mature compensation algorithms. The principle of the proposed method is derived theoretically. The performance of the scheme is analyzed by simulation. The results show that the harmonic induced by timing mismatches can be suppressed by more than 30 dB using the proposed correction scheme.

The total ionizing dose effect in 12-bit, 125 MSPS analog-to-digital converters

This paper presents the total ionizing dose test results at different biases and dose rates for AD9233, which is fabricated using a modern CMOS process. The experimental results show that the digital parts are more sensitive than the other parts. Power down is the worst-case bias, and this phenomenon is first found in the total ionizing dose effect of analog-to-digital converters. We also find that the AC as well as DC parameters are sensitive to the total ionizing dose at a high dose rate, whereas none of the parameters are sensitive at a low dose rate. The test facilities, results and analysis are presented in detail.

Analog-to-digital conversion of information in the retina

We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.