Application Strategy of Digital Comprehensive Management and Maintenance System for Bridges

Effective application of digital integrated management and maintenance systems is essential for successful operation and maintenance management of bridge projects.This article analyzes the application strategy of such systems.It provides an overview of comprehensive digital management and maintenance of bridges,an analysis of the basic components of the integrated management and maintenance system,and its application strategies.This study aims to offer guidance for the application of the system and to improve the quality of modern bridge engineering management and maintenance work.

The Protection of the Right to Equality of the Elderly in the Digital Society

The inequality faced by the elderly in a digital society is the digital inequality caused by both public and private actions,as well as the societal inequality exacerbated by the digital inequality.The essence of this issue lies in the unequal social participation due to the expansion of digital space under digital inequality.The characteristics of the elderly,combined with their inherent human dignity,determine that the ultimate goal of protecting their right to equality in a digital society is not limited to equal digital rights alone.Instead,it aims to ensure that the elderly have equal opportunities for social participation in both digital and non-digital spaces by eliminating digital inequality and curbing the expansion of digital space.This ensures the autonomy of the elderly in the digital society.Accordingly,the State should implement two policies based on both prohibitive obligations that prevent direct infringements and protective obligations that safeguard the equal rights of the elderly against encroachments from private entities.The first policy,“Digital Integration”,empowers the elderly with digital skills and helps them actively integrate into the digital society.The second policy,“Digital Coexistence,”ensures that the elderly can equally participate in society even when they choose to abstain from digital technology.

TEST OF BOARD-LEVEL BOUNDARY SCAN INTEGRITY

The IEEE Standard 1149.1 boundary scan (BS) implementation provides the internal access required for testing the digital printed circuit board (PCB). However, the integrity of the boundary scan test infrastructure should be tested first to guarantee the validation of the results of the rest functional test and diagnosis. This paper describes the fault models and test principles of the BS test access port (TAP) lines on PCBs. A test algorithm with high fault coverage and short time is then presented for the PCB on which all ICs are BS ones.

Accelerating hybrid and compact neural networks targeting perception and control domains with coarse-grained dataflow reconfiguration

Driven by continuous scaling of nanoscale semiconductor technologies,the past years have witnessed the progressive advancement of machine learning techniques and applications.Recently,dedicated machine learning accelerators,especially for neural networks,have attracted the research interests of computer architects and VLSI designers.State-of-the-art accelerators increase performance by deploying a huge amount of processing elements,however still face the issue of degraded resource utilization across hybrid and non-standard algorithmic kernels.In this work,we exploit the properties of important neural network kernels for both perception and control to propose a reconfigurable dataflow processor,which adjusts the patterns of data flowing,functionalities of processing elements and on-chip storages according to network kernels.In contrast to stateof-the-art fine-grained data flowing techniques,the proposed coarse-grained dataflow reconfiguration approach enables extensive sharing of computing and storage resources.Three hybrid networks for MobileNet,deep reinforcement learning and sequence classification are constructed and analyzed with customized instruction sets and toolchain.A test chip has been designed and fabricated under UMC 65 nm CMOS technology,with the measured power consumption of 7.51 mW under 100 MHz frequency on a die size of 1.8×1.8 mm^2.

A routing algorithm for FPGAs with time-multiplexed interconnects

Previous studies show that interconnects occupy a large portion of the timing budget and area in FPGAs.In this work,we propose a time-multiplexing technique on FPGA interconnects.In order to fully exploit this interconnect architecture,we propose a time-multiplexed routing algorithm that can actively identify qualified nets and schedule them to multiplexable wires.We validate the algorithm by using the router to implement 20 benchmark circuits to time-multiplexed FPGAs.We achieve a 38%smaller minimum channel width and 3.8%smaller circuit critical path delay compared with the state-of-the-art architecture router when a wire can be time-multiplexed six times in a cycle.

A Low Power Non-Volatile LR-WPAN Baseband Processor with Wake-Up Identification Receiver

The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.

Modeling Digital Evidence Management and Dynamics Using Petri Nets

In all phases of forensic investigation, digital evidence is exposed to external influences and coming into contact with many factors. Legal admissibility of digital evidence is the ability of that evidence being accepted as evidence in a court of law. Life cycle of digital evidence is very complex. In each stage there is more impact that can violate a chain of custody and its integrity. Contact with different variables occurs through a life cycle of digital evidence and can disrupt its integrity. In order for the evidence to be accepted by the court as valid, chain of custody for digital evidence must be kept, or it must be known who exactly came into contact with evidence in each stage of the investigation. This paper presents a dynamics and life cycle of digital evidence. The Petri nets will be proposed and used for modeling and simulation of this process.

A survey of public needs for digital information service in libraries and museums

Purpose:The purpose of the research is to investigate public needs for digital information service in the Chinese libraries and museums and seek ways to help these public service institutions improve their service to meet user needs.Design/methodology/approach:An online questionnaire survey was used to study the publicneeds for digital information service provided by libraries and museums.A total of 474 valid questionnaires were retrieved for analysis.Findings:The primary purpose of using the digital library and museum service was for knowledge acquisition,followed by work or class assignment and leisure and entertainment.Users need one-stop information service that provides information and service in a more integrated form and allows cross-database searching as well.Research limitations:A majority of the respondents were young and middle-aged people who often use the Internet.We would need to increase our sample size and include different groups of users such as children and retirees to make the sample more representative.Practical implications:Libraries and museums should collaborate to provide the users with one-stop digital information service.Meanwhile,the research can serve as a reference source for the future studies of digital library and museum service.Originality/value:Few studies were published on the public needs for digital library and museum service in China.This study bridges the gap and contributes to our understanding of the Chinese users’ needs for digital information service in libraries and museums.

MOSFET-like CNFET based logic gate library for low-power application:a comparative study

The next generation oflogic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLS1. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors （CNFETs） technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely： complementary-CMOS （C-CMOS）, transmission gate （TG）, complementary pass logic （CPL） and Domino logic （DL） styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average powerdelay-product （PDP）. The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.

Digital Geosciences and Quantitative Mineral Exploration

The idea of mineral exploration,which is called"exploration philosophy"in the Western countries,is the thoughts,the methodology,technology,goals and organization that guide mineral exploration.The three basic elements of mineral exploration are"what to find","where to find"and"how to find".The concept of mineral exploration is gradually changing with the development of these three elements that provide a powerful driving force to change mineral exploration concepts,methods and technology.Innovation of mineral exploration concepts is the result of continuing exploration and development keeping pace with the times.The combination of"mathematical geology"and"information technology"can be called"digital geology".Digital geology is the data analysis component of geological science.Geological data science is a science that uses the general methodology of data to study geology based on the characteristics of geological data and the needs of geological field work.Digital mineral exploration is the application of digital geology in mineral exploration to reduce ore-finding uncertainty.

M-LFM:a multi-level fusion modeling method for shape−performance integrated digital twin of complex structure

As a virtual representation of a specific physical asset,the digital twin has great potential for realizing the life cycle maintenance management of a dynamic system.Nevertheless,the dynamic stress concentration is generated since the state of the dynamic system changes over time.This generation of dynamic stress concentration has hindered the exploitation of the digital twin to reflect the dynamic behaviors of systems in practical engineering applications.In this context,this paper is interested in achieving real-time performance prediction of dynamic systems by developing a new digital twin framework that includes simulation data,measuring data,multi-level fusion modeling(M-LFM),visualization techniques,and fatigue analysis.To leverage its capacity,the M-LFM method combines the advantages of different surrogate models and integrates simulation and measured data,which can improve the prediction accuracy of dynamic stress concentration.A telescopic boom crane is used as an example to verify the proposed framework for stress prediction and fatigue analysis of the complex dynamic system.The results show that the M-LFM method has better performance in the computational efficiency and calculation accuracy of the stress prediction compared with the polynomial response surface method and the kriging method.In other words,the proposed framework can leverage the advantages of digital twins in a dynamic system:damage monitoring,safety assessment,and other aspects and then promote the development of digital twins in industrial fields.

Conformal electrodes for on-skin digitalization

On-skin digitalization,streamlining the concept of the“human to device to cyberspace”platform,has attracted great attention due to its vital function in remote medicine and human-cyber interfaces.Beyond traditional rigid electrodes,soft electrodes with conformal and comfortable interfaces are essential for long-term and high-fidelity signal acquisition.In addition,the on-skin data processing systems will get rid of complex cables toward a vision of fascinating form,being lightweight,skin-friendly and even imperceptible.Although numerous soft materials and devices with mechanical tolerance have been developed,the study of conformal electrodes and on-skin digital integrated systems are still in infancy.Here,the requirements and designs of conformal electrodes,the emerging opportunities and challenges from multichannel/multifunctional sensors to a whole new on-skin sensing platform are highlighted.

Towards a shape-performance integrated digital twin for lumbar spine analysis[version 1;peer review:1 approved,1 not approved]

Background:With significant advancement and demand for digital transformation,the digital twin has been gaining increasing attention as it is capable of establishing real-time mapping between physical space and virtual space.In this work,a shape-performance integrated digital twin solution is presented to predict the real-time biomechanics of the lumbar spine during human movement.Methods:A finite element model(FEM)of the lumbar spine was firstly developed using computed tomography(CT)and constrained by the body movement which was calculated by the inverse kinematics algorithm.The Gaussian process regression was utilized to train the predicted results and create the digital twin of the lumbar spine in real-time.Finally,a three-dimensional virtual reality system was developed using Unity3D to display and record the real-time biomechanics performance of the lumbar spine during body movement.Results:The evaluation results presented an agreement(R-squared>0.8)between the real-time prediction from digital twin and offline FEM prediction.Conclusions:This approach provides an effective method of real-time planning and warning in spine rehabilitation.

A digitally controlled PWM/PSM dual-mode DC/DC converter

A digitally controlled pulse width modulation/pulse skip modulation （PWM/PSM） dual-mode buck DC/DC converter is proposed. Its operation mode can be automatically chosen as continuous conduction mode （CCM） or discontinuous conduction mode （DCM）. The converter works in PSM at DCM and in 2 MHz PWM at CCM. Switching loss is reduced at a light load by skipping cycles. Thus high conversion efficiency is realized in a wide load current. The implementations of PWM control blocks, such as the ADC, the digital pulse width modulator （DPWM） and the loop compensator, and PSM control blocks are described in detail. The parameters of the loop compensator can be programmed for different external component values and switching frequencies, which is much more flexible than its analog rivals. The chip is manufactured in 0.13 μm CMOS technology and the chip area is 1.21 mm^2. Experimental results show that the conversion efficiency is high, being 90% at 200 mA and 67% at 20 mA. Meanwhile, the measured load step response shows that the proposed dual-mode converter has good stability.

CMOS vision sensor with fully digital image process integrated into low power 1/8-inch chip

A digital still camera image processing system on a chip, different from the video camera system, is pre- sented for mobile phone to reduce the power consumption and size. A new color interpolation algorithm is proposed to enhance the image quality. The system can also process fixed patten noise （FPN） reduction, color correction, gamma correction, RGB/YUV space transfer, etc. The chip is controlled by sensor regis- ters by inter-integrated circuit （I2C） interface. The voltage for both the front-end analog and the pad cir- cuits is 2.8 V, and the volatge for the image signal processing is 1.8 V. The chip running under the external 13.5-MHz clock has a video data rate of 30 frames/s and the measured power dissipation is about 75 roW.