THE DESIGN OF AN ALL-DIGITAL PHASE-LOCKED LOOP WITH LOW JITTER BASED ON ISF ANALYSIS

A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.

Design and implementation of digital closed-loop drive control system of a MEMS gyroscope

In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system （MEMS） gyroscope are analyzed in principle. A novel drive circuit for the MEMS gyroscope in digital closed-loop control is proposed, which utilizes a digital phase-locked loop （PLL） in frequency control and an automatic gain control （AGC） method in amplitude control. A digital processing circuit with a field programmable gate array （FPGA） is designed and the experiments are carried out. The results indicate that when the temperature changes, the drive frequency can automatically track the resonant frequency of gyroscope in drive mode and that of the oscillating amplitude holds at a set value. And at room temperature, the relative deviation of the drive frequency is 0.624 ×10^-6 and the oscillating amplitude is 8.0 ×10^-6, which are 0. 094% and 18. 39% of the analog control program, respectively. Therefore, the control solution of the digital PLL in frequency and the AGC in amplitude is feasible.

Analysis and design of DSP-based dual-loop controlled UPS inverters

This paper presents a novel digital dual-loop control scheme of the PWM(PUlse width modulate)inverter. Deadbeat control technique are employed to enhance the performance. Half switching period delayed sampling and control timing strategy is used to improve the system dynamic response. Simulation and experimental results presented in the paper verified the validity of the proposed control scheme.

Optimization of block-floating-point realizations for digital controllers with finite-word-length considerations

The closed-loop stability issue of finite-precision realizations was investigated for digital control-lers implemented in block-floating-point format. The controller coefficient perturbation was analyzed resultingfrom using finite word length (FWL) block-floating-point representation scheme. A block-floating-point FWL closed-loop stability measure was derived which considers both the dynamic range and precision. To facilitate the design of optimal finite-precision controller realizations, a computationally tractable block-floating-point FWL closed-loop stability measure was then introduced and the method of computing the value of this measure for a given controller realization was developed. The optimal controller realization is defined as the solution that maximizes the corresponding measure, and a numerical optimization approach was adopted to solve the resulting optimal realization problem. A numerical example was used to illustrate the design procedure and to compare the optimal controller realization with the initial realization.

Fixed Point Iteration Chaos Controlled ZCDPLL

The stable operation of first and second order Zero Crossing Digital Phase Locked Loop (ZCDPLL) is extended by using a Fixed Point Iteration (FPI) method with relaxation. The non-linear components of ZCDPLL such as sampler phase detector and Digital Controlled Oscillator (DCO) lead to unstable and chaotic operation when the filter gains are high. FPI will be used to stabilize the chaotic operation and consequently extend the lock range of the loop. The proposed stabilized loop can work in higher filter gains which are needed for faster signal acquisition.

基于大创项目的应用技术开发实践——以数字电源教具设计为例

针对教学环节中的难点和重点内容,基于dsPIC33CK256MP505数字信号控制器芯片,为开发新型的数字电源教具,在降压转换器的电路拓扑结构基础上,利用MplabPowerSmart开发软件,完成了电压控制型数字环路补偿器的设计,实现3P3Z数字补偿器的实时算法功能。

正负脉冲电压驱动的电磁螺纹插装阀动态特性分析

提出了一种基于PWM技术的正负脉冲电压控制策略,用于提高锥阀式电磁螺纹插装阀启闭动态响应速度,使其满足数字液压技术的要求。在分析电磁螺纹插装阀结构和工作原理基础上,建立了电磁螺纹插装阀的数学模型,并在AMESim软件中搭建电磁螺纹插装阀及其测试系统的多物理场耦合建模,研究不同正负脉冲电压持续时间条件下电磁螺纹插装阀线圈电流、阀芯位移、电磁力的变化规律,确定了电磁螺纹插装阀响应速度最快时正负脉冲电压控制策略的最优控制参数。利用半实物仿真系统搭建SCV硬件在环测试实验台,对所提正负脉冲控制策略进行验证。实验表明,与常规电压控制策略相比,当正负脉冲电压控制策略中正负脉冲电压持续时间都为10 ms时,电磁螺纹插装阀的开启时间由30 ms缩短到13.5 ms,其关闭时间由139 ms缩短到14 ms。研究结果为电磁螺纹插装阀的高响应化和数字液压技术的发展提供参考。

基于电容电压全前馈的并网逆变器高鲁棒性稳定控制策略

虽然并网逆变器采用电容电压全前馈控制策略,能够有效抑制电网电压背景谐波对并网电流的影响。但是在弱电网工况环境下,由于锁相环、数字控制延时等因素与电网阻抗相互耦合,导致逆变器稳定较差、在阻抗交截频域中呈现弱无源性,易引发系统谐波振荡甚至失稳问题。鉴于此,该文借助无源性理论和阻抗分析方法,深度揭示了影响系统各频带阻抗特性的主导因素,进而提出了一种基于电容电压全前馈的并网逆变器高鲁棒性稳定控制策略。理论分析表明:所提控制策略不仅能有效地拓宽系统输出阻抗稳定范围,还可以保证改进后的系统输出阻抗具有较高的幅值增益。最后,通过仿真和实验验证了所提控制策略的有效性。

大数据驱动下防疫供应链协同机制研究

COVID-19疫情暴露出当前防疫供应链协同机制还存在很大改进空间,亟须深入推进数字化转型。基于供应链运营参考模型,构建面向未来的大数据驱动防疫供应链协同体系,通过计划模拟评估物资需求,采购环节实时监测生产和流通动态,运用优化算法动态调整生产计划,支撑物流路径选择,指导防疫物资合理分配,实现全链条精细化调度,端到端打通信息流,各环节形成闭环控制,使系统具备主动供给和持续自我优化的能力。不仅大幅提高防疫物资配置的响应速度和精准度,还将显著提高供应链主体的协同效率,有助于构建敏锐度高、弹性强的应急保障体系,使之更好地适应疫情防控的严峻形势。

面向悬浮光力系统的集成化反馈控制器研究

悬浮光力系统具有高灵敏度、高稳定性和低耗散等特点,有望发展成为新型高性能力学传感器。针对目前悬浮光力系统存在的反馈控制器兼容性差、软硬件成本高、集成度低等问题,提出了一种兼容多种反馈控制模式的软硬件设计方案,并研制了一套高度集成的反馈控制器,在160 mm×170 mm×42 mm的尺寸上集成了六通道模数/数模转换器、滤波器、现场可编程门阵列+微处理器(FPGA+ARM)等功能模块,并且开发了基于数字锁相环和比例积分微分(PID)控制器的控制算法,最终在同一套硬件系统上实现了跨尺度微粒的运动信息采集和反馈控制,以及数十赫兹至亚兆赫兹的感知带宽。实验结果表明,该集成反馈控制器能够实现超高真空(10-6 Pa量级)下亚微米及微米尺度微粒的稳定悬浮和运动控制。在扩展系统感知带宽的同时减小了整体体积,为悬浮光力传感技术的器件化奠定了基础。

基于Kent映射的数字集群动态负载均衡算法研究

由于动态负载均衡是保证数字集群系统正常运行中不可缺少的环节,但其在控制过程中存在易受通信故障等因素的干扰问题,为此提出基于Kent映射的数字集群动态负载均衡算法。通过基于云平台的虚拟机系统采集数字集群的节点连接数、响应时间、动态负载等信息,分析数字集群系统的负载情况。其次构建数字集群资源利用率模型,通过基于Kent映射的灰狼算法对模型求解得到数字集群的资源利用率。最后将资源利用率输入LQR(Linear Quadratic Regulator)控制回路器中,通过控制服务器的迁移实现数字集群的动态负载均衡。实验结果表明,所提算法处理后的数字集群响应时间短、适应度值大、容错能力强。

Application of novel super-exponential iteration algorithm in underwater acoustic channel

A novel variable step-size modified super-exponential iteration(MSEI)decision feedback blind equalization(DFE)algorithm with second-order digital phase-locked loop is put forward to improve the convergence performance of super-exponential iteration DFE algorithm.Based on the MSEI-DFE algorithm,it is first proposed to develop an error function as an improvement to the error function of MSEI,which effectively achieves faster convergence speed of the algorithm.Subsequently,a hyperbolic tangent function variable step-size algorithm is developed considering the high variation rate of the hyperbolic tangent function around zero,so as to further improve the convergence speed of the algorithm.In the end,a second-order digital phase-locked loop is introduced into the decision feedback equalizer to track and compensate for the phase rotation of equalizer input signals.For the multipath underwater acoustic channel with mixed phase and phase rotation,quadrature phase shift keying(QPSK)and 16 quadrature amplitude modulation(16QAM)modulated signals are used in the computer simulation of the algorithm in terms of convergence and carrier recovery performance.The results show that the proposed algorithm can considerably improve convergence speed and steady-state error,make effective compensation for phase rotation,and efficiently facilitate carrier recovery.

非线性环路补偿的交错并联BUCK变换器数字控制策略研究

针对氢能燃料电池输出低电压、大电流,不能适用通讯基站电源的问题,设计了一种电力电子交错并联BUCK变换器,同时提出了一种非线性环路补偿的数字控制策略。文中采用两个BUCK电路并联,控制信号为180°两相交错脉冲宽度控制,采用小信号模型建立了电压环、电流环数学模型,控制策略采用电流内环、电压外环双闭环控制。为了控制快准稳,分别对两环路控制策略补偿校正设计,通过环路补偿数字控制策略搭建交错并联BUCK变换器simulink模型,仿真结果表明变换器在输入范围下实现了48 V直流稳定输出,验证了本研究的有效性。

激光陀螺机抖控制的DDS锁相频率合成方法及其国产化设计

激光陀螺通常采用数模转换器(DAC)配合模拟乘法器产生正弦自激振荡的机抖控制方式,乘法器模块现阶段没有国产化替代方案,存在自激振荡在高低温条件下偶发不起振问题。因此,选用国产化微处理器MCU配合DAC替换乘法器模块,采用捕获抖动过零信号快速获得控制相位,使用PI控制器进行相位-频率差运算,采取查找表方式实现频率合成,输出周期驱动信号(正弦信号或三角波信号),实现抖动偏频闭环控制。所提方案在某三轴一体小型化三自惯组产品50型陀螺控制系统中应用,实现了关键器件的国产化替代设计,且陀螺系统固定位置百秒计数均值的标准方差优于5‰。

Improved Rotor Flux Observer for Sensorless Control of PMSM with Adaptive Harmonic Elimination and Phase Compensation

In this paper,a sensorless control strategy of a permanent magnet synchronous machine(PMSM)based on an improved rotor flux observer(IFO)is proposed.Due to the unknown integral initial value and the high harmonics caused by current sampling and inverter nonlinearities,the flux linkage estimated by traditional rotor flux observer may be inaccurate.In order to address these issues,a self-adaptive band-pass filter(SABPF)is designed to eliminate the DC component and high-frequency harmonics of the estimated equivalent rotor flux linkage.Furthermore,in order to avoid that the design of PI parameter is influenced by the amplitude of equivalent rotor flux linkage,an improved phase-locked loop(IPLL)is employed to obtain the rotor speed and to normalize the estimated equivalent rotor flux linkage.In addition,angle shift caused by an SABPF is compensated to improve the accuracy of the estimated flux linkage angle.Besides,the parameter robustness of this method is analyzed in detail.Finally,simulation and experimental results demonstrate the effectiveness and parameter robustness of the proposed method.

A time-domain digitally controlled oscillator composed of a free running ring oscillator and flying-adder

A time-domain digitally controlled oscillator （DCO） is proposed. The DCO is composed of a free-running ring oscillator （FRO） and a two lap-selectors integrated flying-adder （FA）. With a coiled cell array which allows uniform loading capacitances of the delay cells, the FRO produces 32 outputs with consistent tap spacing for the FA as reference clocks. The FA uses the outputs from the FRO to generate the output of the DCO according to the control number, resulting in a linear dependence of the output period, instead of the frequency on the digital controlling word input. Thus the proposed DCO ensures a good conversion linearity in a time-domain, and is suitable for time-domain all-digital phase locked loop applications. The DCO was implemented in a standard 0.13μm digital logic CMOS process. The measurement results show that the DCO has a linear and monotonic tuning curve with gain variation of less than 10%, and a very low root mean square period jitter of 9.3 ps in the output clocks. The DCO works well at supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.

NNBI射频功率源输出功率控制系统设计

设计了一种改进型射频功率源输出功率控制系统,解决了现有射频功率源使用中存在的输出功率稳定性与控制精度不足等问题,预期将应用于中国聚变工程实验堆(China Fusion Engineering Test Reactor,CFETR)负离子源中性束系统(Negative Ion Based Neutral Beam Injection System,NNBI)。采用ARM+CPLD双核设计的软、硬件分离控制结构,保障输出功率控制算法运行效率;采用数字化信号控制方法,实现输出功率的高精度控制;通过精确采样射频功率源实际输出功率和闭环功率控制方法设计,实现输出功率的高稳定性控制。对射频功率源样机进行输出功率控制系统模拟负载测试,结果表明:在额定输出功率为50 kW时,输出功率的控制精度高于0.1%、稳定性波动小于0.5%、人机交互软件功能完善。该方案预期可以搭配阻抗匹配网络满足CFETR NNBI射频功率源对输出功率控制的性能要求。

基于DPLL的扫频信号源系统的设计与实现

扫频信号源是输出频率可数控步进调整的正弦波信号源。低相位噪声和杂散的高频谱纯度扫频信号源是组成雷达接收机和系统频域分析设备等的核心。文中以数字锁相环技术(DPLL)作为高频谱纯度信号输出核心,用分频寄存器的设置来控制信号的输出频率,并通过高阶滤波器和自动增益系统得到最终的扫频信号输出频率。电路中,基于ADF4002数字鉴频鉴相器芯片、MC12148压控振荡器芯片和无源滤波器电路构建数字锁相环,再通过VCA821实现自动增益控制电路,最终实现高频谱纯度扫频信号源。经测试,该扫频信号源能在40~120 MHz范围实现较高频谱纯度的扫频信号输出,将DPLL技术应用于扫频信号源不但易于变频和加快扫频源的迭代,而且大幅度降低了硬件开发成本。

基于平均电流模式的同步Buck数字电源设计研究

高效率、高开关频率和数字控制是近年来开关电源领域的研究热点。探讨了基于平均电流模式的同步Buck数字电源设计策略,结合理论分析和Matlab/Simulink软件仿真,分析了同步Buck的环路设计条件,详细阐述了两种电压电流双闭环PI补偿器的设计方法,并提出了一种基于电流环简化的电压环设计方法。使用高性能主流MCU芯片STM32G474作为控制核心,利用高分辨率PWM技术实现200 kHz的开关频率,以中断事件触发和状态机运行思想来构建系统软件的架构。仿真和实验结果表明系统具有效率高、动态响应快和鲁棒性强等特点,为数字电源的通用化设计提供了参考。

三相LCL型并网逆变器双电流环控制器设计

并网逆变器在当前电网中具有举足轻重的地位。本文针对三相LCL型并网逆变器进行了研究,建立了其数学模型,给出了其双电流环控制器的设计方法,并针对于常规双电流环控制稳定裕量低的弊端,提出了一种改进型双电流环控制策略。最后,进行了仿真验证,分析表明,在较为理想的模型下,两种双电流环控制策略均具备较为优秀的控制效果,但在非理想模型下,所提改进型控制策略具备更大的稳定裕量,更适合在实际数字控制系统中应用。