Amplitude quantization is one of the main sources of spurious noise frequencies in Direct Digital Frequency Synthesizers (DDFSs), which affect their application to many wireless telecommu- nication systems. In this pa...Amplitude quantization is one of the main sources of spurious noise frequencies in Direct Digital Frequency Synthesizers (DDFSs), which affect their application to many wireless telecommu- nication systems. In this paper, two different kinds of spurious signals due to amplitude quantization in DDFSs are exactly formulated in the time domain and detailedly compared in the frequency do- main, and the effects of the DDFS parameter variations on the spurious performance are thoroughly studied. Then the spectral properties and power levels of the amplitude-quantization spurs in the absence of phase-accumulator truncation are emphatically analyzed by waveform estimation and computer simulation, and several important conclusions are derived which can provide theoretical support for parameter choice and spurious performance evaluation in the application of DDFSs.展开更多
An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequen- cy synthesizer is based on a direct digital synthesizer （ DDS ） -driven wideband phase-locked loop （PLL） architecture which...An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequen- cy synthesizer is based on a direct digital synthesizer （ DDS ） -driven wideband phase-locked loop （PLL） architecture which can achieve low spurious noise and rapid frequency hopping simultaneous- ly. The mechanism of introducing high level spurs by the images of DDS digital to analog convertor （DAC） output is analyzed. A novel DDS frequency planning method is proposed to ensure low col- ored noise within the entire bandwidth. The designed output frequency range is 3. 765 -4. 085 GHz, and the step size is 5 MHz with frequency agility of less than 1 μs. Measured results demonstrate that the average spurious free dynamic range （SFDR） is about 64 dBc in a 320 MHz bandwidth.展开更多
文章主要介绍一种现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)控制数字频率合成器(Direct Digital Synthesizer,DDS)实现四进制移频键控(Quaternary Frequency Shift Keying,4FSK)&频率调制(Frequency Modulation,FM...文章主要介绍一种现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)控制数字频率合成器(Direct Digital Synthesizer,DDS)实现四进制移频键控(Quaternary Frequency Shift Keying,4FSK)&频率调制(Frequency Modulation,FM)调制载波的设计方案,给出技术指标参数、硬件组成框图以及信号处理流程,对4FSK的调制信号和FM信号产生的实施方法进行探讨,并对电路框图中的关键器件进行国产化设计选型。展开更多
为满足现代电子测量和无线电通信领域对激励源的需求,采用DDS(Direct Digital Synthesizer)芯片AD9854ASVZ设计一款高频率高精度信号发生器。ARM Cortex-M3内核的STM32F103VE芯片作为系统的MCU(Microcontroller Unit);在MDK-ARM平台下用...为满足现代电子测量和无线电通信领域对激励源的需求,采用DDS(Direct Digital Synthesizer)芯片AD9854ASVZ设计一款高频率高精度信号发生器。ARM Cortex-M3内核的STM32F103VE芯片作为系统的MCU(Microcontroller Unit);在MDK-ARM平台下用C语言开发主监控程序和信号产生程序;利用Python工具在PC(Personal Computer)端编写人机交互界面,通过串口实现PC与MCU之间通信;设计低通滤波电路和多级放大电路对产生的信号进行噪声(杂散)抑制和幅度控制。测试结果表明,该信号发生器输出信号失真小,精度高,频率范围宽,具备较好的稳定性。输出正弦波、方波的频率范围为DC^150 MHz,频率漂移100 PPB(Part Per Billion),频率分辨率1μHz,输出信号幅度峰峰值可在10 m V^20 V范围内,以10 m V步进调节。技术指标满足大部分外场实验和工业应用的需求。展开更多
基金Supported by National High-Technology Research and Development Plan of China (Grant No.2006AA01Z452)
文摘Amplitude quantization is one of the main sources of spurious noise frequencies in Direct Digital Frequency Synthesizers (DDFSs), which affect their application to many wireless telecommu- nication systems. In this paper, two different kinds of spurious signals due to amplitude quantization in DDFSs are exactly formulated in the time domain and detailedly compared in the frequency do- main, and the effects of the DDFS parameter variations on the spurious performance are thoroughly studied. Then the spectral properties and power levels of the amplitude-quantization spurs in the absence of phase-accumulator truncation are emphatically analyzed by waveform estimation and computer simulation, and several important conclusions are derived which can provide theoretical support for parameter choice and spurious performance evaluation in the application of DDFSs.
基金Supported by the Fund of National Defense Industry Innova-tive Team(231)
文摘An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequen- cy synthesizer is based on a direct digital synthesizer （ DDS ） -driven wideband phase-locked loop （PLL） architecture which can achieve low spurious noise and rapid frequency hopping simultaneous- ly. The mechanism of introducing high level spurs by the images of DDS digital to analog convertor （DAC） output is analyzed. A novel DDS frequency planning method is proposed to ensure low col- ored noise within the entire bandwidth. The designed output frequency range is 3. 765 -4. 085 GHz, and the step size is 5 MHz with frequency agility of less than 1 μs. Measured results demonstrate that the average spurious free dynamic range （SFDR） is about 64 dBc in a 320 MHz bandwidth.
文摘文章主要介绍一种现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)控制数字频率合成器(Direct Digital Synthesizer,DDS)实现四进制移频键控(Quaternary Frequency Shift Keying,4FSK)&频率调制(Frequency Modulation,FM)调制载波的设计方案,给出技术指标参数、硬件组成框图以及信号处理流程,对4FSK的调制信号和FM信号产生的实施方法进行探讨,并对电路框图中的关键器件进行国产化设计选型。
文摘为满足现代电子测量和无线电通信领域对激励源的需求,采用DDS(Direct Digital Synthesizer)芯片AD9854ASVZ设计一款高频率高精度信号发生器。ARM Cortex-M3内核的STM32F103VE芯片作为系统的MCU(Microcontroller Unit);在MDK-ARM平台下用C语言开发主监控程序和信号产生程序;利用Python工具在PC(Personal Computer)端编写人机交互界面,通过串口实现PC与MCU之间通信;设计低通滤波电路和多级放大电路对产生的信号进行噪声(杂散)抑制和幅度控制。测试结果表明,该信号发生器输出信号失真小,精度高,频率范围宽,具备较好的稳定性。输出正弦波、方波的频率范围为DC^150 MHz,频率漂移100 PPB(Part Per Billion),频率分辨率1μHz,输出信号幅度峰峰值可在10 m V^20 V范围内,以10 m V步进调节。技术指标满足大部分外场实验和工业应用的需求。
