Gate leakage current of NMOSFET with ultra-thin gate oxide

As dimensions of the metal-oxide-semiconductor field-effect transistor (MOSFET) are scaling down and the thickness of gate oxide is decreased,the gate leakage becomes more and more prominent and has been one of the most important limiting factors to MOSFET and circuits lifetime.Based on reliability theory and experiments,the direct tunneling current in lightly-doped drain (LDD) NMOSFET with 1.4 nm gate oxide fabricated by 90 nm complementary metal oxide semiconductor (CMOS) process was studied in depth.High-precision semiconductor parameter analyzer was used to conduct the tests.Law of variation of the direct tunneling (DT) current with channel length,channel width,measuring voltage,drain bias and reverse substrate bias was revealed.The results show that the change of the DT current obeys index law;there is a linear relationship between gate current and channel dimension;drain bias and substrate bias can reduce the gate current.

高k栅介质MOSFET的栅电流模型(英文)

提出了包括有限势垒高度下反型层量子化效应以及多晶硅耗尽效应在内的直接隧穿电流模型 .在该模型的基础上 ,研究了采用不同高介电常数栅介质材料时MOSFET的栅电流与介质材料的介电常数、禁带宽度及和Si导带不连续等参数之间的关系 .所获得的结果能够为新型栅介质材料的选取提供依据 .

直接栅MOSFET静电场传感器温度漂移模型和模拟

推导出了直接栅MOSFET静电场传感器的温度漂移系数,并研究了温度漂移的主要原因。此研究工作对消除直接栅MOSFET静电场传感器的温度漂移有一定的帮助。首先,建立了直接栅MOSFET静电场传感器沟道中电荷随温度变化的模型。其次,根据直接栅MOSFET沟道载流子浓度和载流子迁移率都为温度的函数,将直接栅MOSFET静电场传感器的温度漂移定义为由沟道载流子迁移率随温度变化引起的温度漂移系数αμ和由沟道载流子浓度随温度变化引起的温度漂移系数αQ,并对它们与温度的关系作了推导和研究。最后,对沟道载流子迁移率随温度变化引起的温度漂移系数αμ和由沟道载流子浓度随温度变化引起的温度漂移系数αQ进行了模拟和比较。模拟结果表明,温度漂移系数αμ远小于温度漂移系数αQ。因此沟道载流子浓度随温度变化是直接栅MOSFET静电场传感器的温度漂移的主要原因。

Analytical modeling of the direct tunneling current through high-k gate stacks for long-channel cylindrical surrounding-gate MOSFETs

An analytical direct tunneling gate current model for cylindrical surrounding gate（CSG） MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gate＇s oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current.Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.

超薄栅氧MOS器件传统关态栅泄漏电流研究

理论分析了MOSFET关态泄漏电流产生的物理机制,深入研究了栅氧化层厚度为1.4nm MOSFET传统关态下边缘直接隧穿栅泄漏现象.结果表明:边缘直接隧穿电流服从指数变化规律;传统关态下边缘直接隧穿对长沟道器件的影响大于短沟道器件;衬底反偏在一定程度上减小边缘直接隧穿泄漏电流.

深亚微米MOS器件中栅介质层的直接隧穿电流(英文)

在 WKB近似的理论框架下 ,提出了一个 MOS器件中栅介质层直接隧穿电流的模型 .在这个模型中 ,空穴量子化采用了一种改进的单带有效质量近似方法 ,这种方法考虑了价带的混合效应 .通过与试验结果的对比 ,证明了这个模型可以适用于 CMOS器件中电子和空穴的隧穿电流 .还研究了介质层能隙中的色散对隧穿电流的影响 .

直接隧穿栅电流对CMOS逻辑电路的影响

对于纳米级的CMOS电路,由于MOS器件具有超薄的氧化层,栅隧穿漏电流的存在严重地影响了电路的正常工作。本文基于可靠性理论和电路级仿真深入地研究直接隧穿电流对CMOS逻辑电路的影响。仿真结果很好地与理论分析相符合,这些理论和仿真将有助于以后的集成电路设计。

MOS器件直接隧穿栅电流及其对CMOS逻辑电路的影响

随着晶体管尺寸按比例缩小,越来越薄的氧化层厚度导致栅上的隧穿电流显著地增大,严重地影响器件和电路的静态特性,为此,基于可靠性理论和仿真,对小尺寸MOSFET(metal-oxide-semiconductor field effect transistor)的直接隧穿栅电流进行研究,并通过对二输入或非门静态栅泄漏电流的研究,揭示直接隧穿栅电流对CMOS(complementary metal oxide semiconductor)逻辑电路的影响。仿真工具为HSPICE软件,MOS器件模型参数采用的是BSIM4和LEVEL 54,栅氧化层厚度为1.4 nm。研究结果表明:边缘直接隧穿电流是小尺寸MOS器件栅直接隧穿电流的重要组成成分;漏端偏置和衬底偏置通过改变表面势影响栅电流密度;CMOS逻辑电路中MOS器件有4种工作状态,即线性区、饱和区、亚阈区和截止区;CMOS逻辑电路中MOS器件的栅泄漏电流与其工作状态有关。仿真结果与理论分析结果较符合,这些理论和仿真结果有助于以后的集成电路设计。