Analytical modeling of the direct tunneling current through high-k gate stacks for long-channel cylindrical surrounding-gate MOSFETs

An analytical direct tunneling gate current model for cylindrical surrounding gate（CSG） MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gate＇s oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current.Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO_2/high-k gate stacked dielectric

A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor（DGJLT） for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO2. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset,workfunction difference and k-values on the tunneling current of the DGJLT.

Generation of mid-infrared supercontinuum by designing circular photonic crystal fiber

A circular photonic crystal fiber(C-PCF)based on As2 Se3 is designed,which has three zero dispersion wavelengths and flat dispersion.Using this fiber,a wide mid-infrared supercontinuum(MIR-SC)can be generated by launching a femtosecond pulse in the first anomalous dispersion region.The simulation results show that the MIR-SC is formed by soliton self-frequency shift and direct soliton spectrum tunneling on the long wavelength side and self-phase modulation,soliton fission on the short wavelength side.Further,optical shocking and four-wave mixing(FWM)are not conducive to the long-wavelength extension of MIR-SC,while the number and intensity of fundamental solitons have a greater effect on the short-wavelength extension of MIR-SC.The generation of optical shocking waves,FWM waves and fundamental solitons can be obviously affected by changing the fiber length and input pulse parameters,so that the spectrum range and flatness can be adjusted with great freedom.Finally,under the conditions of 4000 W pulse peak power,30 fs pulse width,47 mm fiber length,and 0 initial chirp,a wide MIR-SC with a coverage range of 2.535μm-16.6μm is obtained.These numerical results are encouraging because they demonstrate that the spread of MIR-SC towards the red and blue ends can be manipulated by choosing the appropriate incident pulse and designing optimized fiber parameters,which contributes to applications in such diverse areas as spectroscopy,metrology and tomography.

Degradation of ultra-thin gate oxide LDD NMOSFET under GIDL stress

The degradation of device under GIDL （gate-induced drain leakage current） stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides. Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg. The characteristics of the GIDL current are used to analyze the damage generated during the stress. It is clearly found that the change of GIDL current before and after stress can be divided into two stages. The trapping of holes in the oxide is dominant in the first stage, but that of electrons in the oxide is dominant in the second stage. It is due to the common effects of edge direct tunneling and band-to-band tunneling. SILC（stress induced leakage current）in the NMOSFET decreases with increasing stress time under GIDL stress. The degradation characteristic of SILC also shows saturating time dependence. SILC is strongly dependent on the measured gate voltage. The higher the measured gate voltage, the less serious the degradation of the gate current. A likely mechanism is presented to explain the origin of SILC during GIDL stress.