The change characteristics of the calculated wind wave fields near lateral boundaries with SWAN model

Since the wind wave model Simulating Waves Nearshore （SWAN） cannot effectively simulate the wave fields near the lateral boundaries, the change characteristics and the distortion ranges of calculated wave factors including wave heights, periods, directions, and lengths near the lateral boundaries of calculation domain are carefully studied in the case of different water depths and wind speeds respectively. The calculation results show that the effects of the variety of water depth and wind speed on the modeled different wave factors near the lateral boundaries are different. In the case of a certain wind speed, the greater the water depth is, the greater the distortion range is. In the case of a certain water depth, the distortion ranges defined by the relative errors of wave heights, periods, and lengths are different from those defined by the absolute errors of the corresponding wave factors. Moreover, the distortion ranges defined by the relative errors decrease with the increase of wind speed; whereas the distortion ranges defined by the absolute errors change a little with the variety of wind speed. The distortion range of wave direction decreases with the increase of wind speed. The calculated wave factors near the lateral boundaries with the SWAN model in the actual physical areas, such as Lake Taihu and Lake Dianshan considered in this study, are indeed distorted if the calculation domains are not enlarged on the basis of actual physical areas. Therefore, when SWAN is employed to calculate the wind wave fields near the shorelines of sea or inland lakes, the appropriate approaches must be adopted to reduce the calculation errors.

High performance 14-bit pipelined redundant signed digit ADC

A novel architecture of a pipelined redundant-signed-digit analog to digital converter（RSD-ADC） is presented featuring a high signal to noise ratio（SNR）, spurious free dynamic range（SFDR） and signal to noise plus distortion（SNDR） with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC（residue amplification circuit）stages. With the proposed architecture of ADC, SNDR obtained is 85.89 d B, SNR is 85.9 d B and SFDR obtained is 102.8 d B at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.