BALANCED TRUNCATED MODELS OF C INTERCONNECT CIRCUITS AND THEIR SIMULATION

The Balanced Truncation Method (BTM) is applied to an even distributed RC interconnect case by using Wang's closed-forms of even distributed RC interconnect models. The results show that extremely high order RC interconnect can be high-accurately approximated by only third order balanced model. Related simulations are executed in both time domain and frequency domain. The results may be applied to VLSI interconnect model reduction and design.

Density Matrix for Mesoscopic Distributed Parameter Circuits

Under the Born-von-Karmann periodic boundary condition, we propose a quantization scheme for non-dissipative distributed parameter circuits (i.e. a uniform periodic transmission line). We find the unitary operator for diagonalizing the Hamiltonian of the uniform periodic transmission line. The unitary operator is expressed in a coordinate representation that brings convenience to deriving the density matrix rho(q,q',beta). The quantum fluctuations of charge and current at a definite temperature have been studied. It is shown that quantum fluctuations of distributed parameter circuits, which also have distributed properties, are related to both the circuit parameters and the positions and the mode of signals and temperature T. The higher the temperature is, the stronger quantum noise the circuit exhibits.

Improved high-frequency equivalent circuit model based on distributed effects for SiGe HBTs with CBE layout

In this paper, we present an improved high-frequency equivalent circuit for SiGe heterojunction bipolar transistors（HBTs） with a CBE layout, where we consider the distributed effects along the base region. The actual device structure is divided into three parts： a link base region under a spacer oxide, an intrinsic transistor region under the emitter window,and an extrinsic base region. Each region is considered as a two-port network, and is composed of a distributed resistance and capacitance. We solve the admittance parameters by solving the transmission-line equation. Then, we obtain the smallsignal equivalent circuit depending on the reasonable approximations. Unlike previous compact models, in our proposed model, we introduce an additional internal base node, and the intrinsic base resistance is shifted into this internal base node,which can theoretically explain the anomalous change in the intrinsic bias-dependent collector resistance in the conventional compact model.

Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit

This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter （ADC） A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm^2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.