基于归一分解的并行多目标Dividing Rectangles算法

多目标优化问题普遍存在且难以解决,目前多采用多目标进化算法进行求解.然而,这些方法通常在种群初始化阶段和进化过程中包含随机操作以保持多样性,导致了其结果不可复现且缺乏全局收敛的理论保证.鉴于此,提出了一种基于归一分解的多目标Dividing Rectangles(DIRECT)算法,首先通过一种可较好捕捉复杂前沿的归一分解方法将原问题分解为一系列子问题,以降低问题计算复杂度;其次,采用Dividing Rectangles算法同时优化分解得到的子问题,并在优化过程中基于全局关联机制将生成的候选解分配给相应的子问题,以更好地保留优秀候选解并提高算法搜索效率;最后,证明了算法的收敛性.此外,为了进一步提高计算效率,提出了一种基于自适应关联迁移策略的多层次多粒度并行方案,并基于该方案对所提出的算法进行了并行化.将所提算法应用于多个基准优化问题,实验结果表明,相比于NSGA-II,所提串行算法能够产生收敛性、多样性更为优越的帕累托最优解集,并行算法可在大规模缩短问题求解时间的同时,进一步提升帕累托前沿近似精度.

Does digitalization mitigate regional inequalities?Evidence from China

Regional inequality significantly influences sustainable development and human well-being.In China,there exists pronounced regional disparities in economic and digital advancements;however,scant research delves into the interplay between them.By analyzing the economic development and digitalization gaps at regional and city levels in China,extending the original Cobb-Douglas production function,this study aims to evaluate the impact of digitalization on China's regional inequality using seemingly unrelated regression.The results indicate a greater emphasis on digital inequality compared to economic disparity,with variable coefficients of 0.59 for GDP per capita and 0.92 for the digitalization index over the past four years.However,GDP per capita demonstrates higher spatial concentration than digitalization.Notably,both disparities have shown a gradual reduction in recent years.The southeastern region of the Hu Huanyong Line exhibits superior levels and rates of economic and digital advancement in contrast to the northwestern region.While digitalization propels economic growth,it yields a nuanced impact on achieving balanced regional development,encompassing both positive and negative facets.Our study highlights that the marginal utility of advancing digitalization is more pronounced in less developed regions,but only if the government invests in the digital infrastructure and education in these areas.This study's methodology can be utilized for subsequent research,and our findings hold the potential to the government's regional investment and policy-making.

Yellowstone Region Drainage History as Determined from the 1955 Ashton, Idaho, Montana, and Wyoming 1:250,000 Scale Topographic Map, USA

The United States Geological Survey (USGS) 1955 (revised in 1972) Ashton topographic map (Ashton map) with a 1:250,000 scale and a 200-foot (about 60-meter) contour interval covers almost all of Yellowstone National Park and some adjacent regions to the south and west. In spite of numerous publications discussing Yellowstone region geologic history the drainage system and erosional landform evidence on the Ashton map appears to have been ignored. Drainage divides identifiable on the Ashton map separate the north-oriented Yellowstone, Gallatin, Madison, and Jefferson River drainage basins (which are located to the north and east of the continental divide with their water flowing to the Missouri River and ultimately the Gulf of Mexico) from the south-oriented Snake River drainage basin (with its water eventually reaching the Pacific Ocean). The Ashton map shows water-eroded passes and through valleys which link diverging and converging valleys which drain in opposite directions from the continental divide. These diverging and converging valleys suggest large volumes of south-oriented water once flowed across the Yellowstone region continental divide and some other Ashton map drainage divides. The accepted geology and glacial history paradigm (accepted paradigm) cannot satisfactorily explain the Ashton map drainage system and erosional landform evidence, which may be why geomorphologists have never addressed the map evidence. A new and fundamentally different geology and glacial history paradigm requiring the Yellowstone region to be located on the rim of a continental ice sheet created and occupied deep “hole” (which was uplifted as immense meltwater floods flowed across it) explains Ashton map drainage system and erosional landform evidence, but raises questions about previously published Yellowstone region geologic histories.

Divide and recombine approach for warranty database: estimating the reliability of an automobile component

The continuously updated database of failures and censored data of numerous products has become large, and on some covariates, information regarding the failure times is missing in the database. As the dataset is large and has missing information, the analysis tasks become complicated and a long time is required to execute the programming codes. In such situations, the divide and recombine (D&R) approach, which has a practical computational performance for big data analysis, can be applied. In this study, the D&R approach was applied to analyze the real field data of an automobile component with incomplete information on covariates using the Weibull regression model. Model parameters were estimated using the expectation maximization algorithm. The results of the data analysis and simulation demonstrated that the D&R approach is applicable for analyzing such datasets. Further, the percentiles and reliability functions of the distribution under different covariate conditions were estimated to evaluate the component performance of these covariates. The findings of this study have managerial implications regarding design decisions, safety, and reliability of automobile components.

Analysis of Mobile and Internet Network Coverage: Propagation of Electromagnetic Waves and Concept of Digital Divide in Burundi

Mobile and Internet network coverage plays an important role in digital transformation and the exploitation of new services. The evolution of mobile networks from the first generation (1G) to the 5th generation is still a long process. 2G networks have developed the messaging service, which complements the already operational voice service. 2G technology has rapidly progressed to the third generation (3G), incorporating multimedia data transmission techniques. It then progressed to fourth generation (4G) and LTE (Long Term Evolution), increasing the transmission speed to improve 3G. Currently, developed countries have already moved to 5G. In developing countries, including Burundi, a member of the East African Community (ECA) where more than 80% are connected to 2G technologies, 40% are connected to the 3G network and 25% to the 4G network and are not yet connected to the 5G network and then still a process. The objective of this article is to analyze the coverage of 2G, 3G and 4G networks in Burundi. This analysis will make it possible to identify possible deficits in order to reduce the digital divide between connected urban areas and remote rural areas. Furthermore, this analysis will draw the attention of decision-makers to the need to deploy networks and coverage to allow the population to access mobile and Internet services and thus enable the digitalization of the population. Finally, this article shows the level of coverage, the digital divide and an overview of the deployment of base stations (BTS) throughout the country to promote the transformation and digital inclusion of services.

Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer

An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler （DMP） and programmable ＆ pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively. Using a DMP high speed, lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps. The flexibility and reusability of the progrs, mmable divider is high;its use could be extended to many complicated frequency synthesizers. By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.

A Programmable 2.4GHz CMOS Multi-Modulus Frequency Divider

A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 prescaler and by 128-255 multi-modulus frequency divider. In the circuit design, power and speed trade-offs are analyzed for the prescaler, and power optimization techniques are used according to the input frequency of each divider cell for the 128-255 multimodulus frequency divider. The chip is designed with ESD protected I/O PAD. The dividers chain can work as high as 2.4GHz with a single ended input signal and beyond 2.6GHz with differential input signals. The dual-modulus prescaler consumes 11mA of current while the 128-255 multi-modulus frequency divider consumes 17mA of current with a 3.3V power supply. The core area of the die without PAD is 0.65mm × 0.3mm. This programmable multi-modulus frequency divider can be used for 2.4GHz ISM band PLL-based frequency synthesizers. To our knowledge, this is the first reported multi-modulus frequency divider with this structure in China.

A Novel High-Voltage Detector Integrated into SPIC by Using FFLR

A novel high voltage detector that can be integrated into SPIC (Smart Power IC) is proposed.The structure is designed on the basis of normal junction terminal technique of FFLR (Floating Field Limiting Rings) system.The field limiting ring as a voltage divider,is used to optimize the surface field.The voltage of main junction increases from 0 to a high value,while the utmost ring is designed to vary within a small range,which can be handled by using low voltage logic circuits.An example of 400V rings system is analyzed and simulated for this structure.The results prove that the high voltage detector can detect high voltage in SPIC.The structure can be integrated into SPIC.Besides,it is compatible with CMOS or BCD(Bipolar CMOS Dmos) technology,without any additional processes required.

基于Dividing Rectangles的多模态医学图像配准算法

为了准确、可靠地配准多模态医学图像,提出了一种基于互信息的全局优化配准算法。该算法首先提取出目标物体的外轮廓面,再用迭代最近点方法初步对齐图像;然后用确定性的全局优化方法—Dividing Rectangles搜索归一化互信息的全局最优解。该算法利用图像的特征信息,为Dividing Rectangles方法提供了一个较好的初始配准位置,并充分利用了Dividing Rectangles方法在小范围内的高效搜索能力。实验结果表明,对于3维人体脑部数据,该算法配准精度高、速度快,而且有效地避免了配准过程中出现的局部极值。

Integrated Low-Power CMOS VCO and Its Divide-by-2 Dividers

An integrated low power CMOS VCO and its divide by 2 dividers for WLAN transceivers are presented.The VCO is based on on chip symmetrical spiral inductor and differential diode and the divide by 2 dividers are based on the ILFD technique.Due to differential LC tanks and ILFD techniques,power consumption is low.The circuit is implemented in a 0 18μm CMOS process.Measurements show the proposed circuit could produce 3 6/1 8GHz dual band LO signals with a wide tuning range and low phase noise.1 8GHz LO signals are quadrature.It consumes 5mA at V DD =1 5V.The size of die area is only 1 0mm×1 0mm.

Low Jitter,Dual-Modulus Prescalers for RF Receivers

Dual-modulus prescalers （DMP） for RF receivers are studied. An improved D-latch is proposed to increase the speed and the driving capability of the DMP. A novel D-latch architecture integrated with ‘OR＇ logic is proposed to decrease the complexity of the circuit. A divided-by-16/17 DMP for application in a digital video broadcasting-terrestrial receiver is realized with a TSMC 0.18μm mixed-signal CMOS process. The programmable ＆ pulse swallow divider in this receiver is designed with a 0.18μm CMOS standard cell library and realized in the same process. The measured results show that the DMP has an output jitter of less than 0.03% and works well with the programmable ＆ pulse swallow divider.

Key technologies of frequency-hopping frequency synthesizer for Bluetooth RF front-end

A scheme of a frequency-hopping frequency-synthesizer applied to a Bluetooth ratio frequency （RF） front-end is presented,and design of a voltage controlled oscillator （VCO） and dual-modulus prescaler are focused on.It is fabricated in a 0.18 μm mixed-signal CMOS （complementary metal-oxide-semiconductor transistor） process.The power dissipation of VCO is low and a stable performance is gained.The measured phase noise of VCO at 2.4 GHz is less than -114.32 dBc/Hz.The structure of the DMP is optimized and a novel D-latch integrated with ＂OR＂ logic gate is used.The measured results show that the chip can work well under a 1.8 V power supply.The power dissipation of the core part in a dual modulus prescaler is only 5.76 mW.An RMS jitter of 2 ps is measured on the output signal at 118.3 MHz.It is less than 0.02% of the clock period.

Frequency synthesizer for DRM/DAB/AM/FM RF front-end

This paper describes a wideband low phase noise frequency synthesizer.It operates in the multi-band including digital radio mondiale DRM digital audio broadcasting DAB amplitude modulation AM and frequency modulation FM .In order to cover the signals of the overall frequencies a novel frequency planning and a new structure are proposed. A wide-band low-phase-noise low-power voltage-control oscillator VCO and a high speed wide band high frequency division ratio pulse swallow frequency divider with a low power consumption are presented.The monolithic DRM/DAB/AM/FM frequency synthesizer chip is also fabricated in a SMIC＇s 0.18-μm CMOS process.The die area is 1 425 μm ×795 μm including the test buffer and pads. The measured results show that the VCO operating frequency range is from 2.22 to 3.57 GHz the measured phase noise of the VCO is 120.22 dBc/Hz at 1 MHz offset the pulse swallow frequency divider operation frequency is from 0.9 to 3.4 GHz.The phase noise in the phase-locked loop PLL is-59.52 dBc/Hz at 10 kHz offset and fits for the demand of the DRM/DAB/AM/FM RF front-end. The proposed frequency synthesizer consumes 47 mW including test buffer under a 1.8 V supply.

0.18μm CMOS programmable frequency divider design for DVB-T

The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communication systems, is presented. By cooperating with a dual-modulus prescaler, this divider can realize an integer frequency division from 926 to 1 387. Besides the traditional standard cell design flow, such as logic synthesis, placement and routing, the interactions between front-end and back-end are also considered to optimize the design flow under deep submicron technology. By back-annotating the back-end information to front-end design, a custom wire-load model is created which is more practical compared with the default model. This divider has been fabricated in TSMC 0. 18μm CMOS technology using Artisan standard cell library. The chip area is 675 μm × 475 μm and the power consumption is about 2 mW under a 1.8 V power supply. Measurement results show that it works correctly and can realize a frequency division with high precision.

中国中部农村“数字鸿沟”研究——以安徽省、湖北省两村庄为例

数字鸿沟(digital divide),也译为数码沟,借鉴学者祝建华的观点,数字鸿沟的概念为"社会各阶层之间在使用互联网上的差别"。①Attewell将"数字鸿沟"更为具体地划分为"一级鸿沟"和"二级鸿沟"。②通常情况下,我们也将其称为"接入沟"和"使用沟"。一级鸿沟指"电脑或互联网接入上存在的差距","二级鸿沟"指个人在互联网使用上存在的差距。当前学界对于数字鸿沟的研究主要是国家与国家之间、城乡之间的数字鸿沟问题,方法上以逻辑陈述居多。

基于HyperSim的网格调度模拟

由于网格环境的复杂、动态和自治性等特点,研究网格任务调度算法时,高性能的网格模拟器是不可缺的。首先介绍了HyperSim(全数字实时仿真器)的特点,通过对比其它模拟器说明使用HyperSim的理由。然后,针对调度算法中最经典的Min-Min算法进行了分析,指出了该算法中存在的负载不平衡的缺点,并在该算法的基础上提出了一个改进的Divided-Min-Min算法。最后采用HyperSim对所提出的算法进行仿真,验证算法的合理性和高效性。

An 8.5GHz 1∶8 Frequency Divider in 0.35μm CMOS Technology

An 1∶8 frequency divider is designed and realized in a 0 35μm standard CMOS technology.The chip consists of three stages of 1∶2 divider cells,which are constructed with source couple logic (SCL) flip flops.By revising the traditional topology of SCL flip flop,a divider with better performances is got.The results of measurement show that the whole chip achieves the frequency division at more than 8 5GHz.Each 1∶2 divider consumes about 11mW from a 3 3V supply.The divider can be used in RF and optic fiber transceivers and other high speed systems.

Bridging Digital Divide for English Learners at Chinese Secondary Schools

This article reviews the concept of digital divide and particularly discusses the digital divide among K-12 students in rural and urban China,as well as the e-learning strategies initiated by the Chinese government that were designed to minimize this digital divide in China.This article concludes by explaining the issue of skills on effective e-learning and correspondingly making suggestions for English teachers in K-12 schools in China.

Gene transfer and therapy with adenoviral vector in rats with diethylnitrosamine-induced hepatocellular carcinoma

Viral-mediated gene transfer of thymidine kinase ofherpes simplex virus (HSV-tk) has been used to confercytotoxic sensitivity to ganciclovir (GCV) in a variety oftnmor cells. HSV-tk converts GCV into a phosphorylatedcompound which is toxic for dividing cells by blockingDNA synthesis. Our previous study has shown

Design of a Frequency Divider with Reduced Complexity Based on a Resonant Tunneling Diode

A novel edge-triggered D-flip-flop based on a resonant tunneling diode （RTD） is proposed and used to construct a binary frequency divider. The design is discussed in detail and the performance of the circuit is verified using SPICE. Relying on the nonlinear characteristics of RTD,we reduced the number of components used in our DFF circuit to only half of that required using conventional CMOS SCFL technology.