It is a well-known fact that test power consumption may exceed that during functional operation. Leakage power dissipation caused by leakage current in Complementary Metal-Oxide-Semiconductor （CMOS） circuits during ...It is a well-known fact that test power consumption may exceed that during functional operation. Leakage power dissipation caused by leakage current in Complementary Metal-Oxide-Semiconductor （CMOS） circuits during test has become a significant part of the total power dissipation. Hence, it is important to reduce leakage power to prolong battery life in portable systems which employ periodic self-test, to increase test reliability and to reduce test cost. This paper analyzes leakage current and presents a kind of leakage current simulator based on the transistor stacking effect. Using it, we propose techniques based on don＇t care bits （denoted by Xs） in test vectors to optimize leakage current in integrated circuit （IC） test by genetic algorithm. The techniques identify a set of don＇t care inputs in given test vectors and reassign specified logic values to the X inputs by the genetic algorithm to get minimum leakage vector （MLV）. Experimental results indicate that the techniques can effectually optimize leakage current of combinational circuits and sequential circuits during test while maintaining high fault coverage,展开更多
This paper proposes an effective method for reducing test data volume undermultiple scan chain designs. The proposed method is based on reduction of distinct scan vectorsusing selective don't-care identification. ...This paper proposes an effective method for reducing test data volume undermultiple scan chain designs. The proposed method is based on reduction of distinct scan vectorsusing selective don't-care identification. Selective don't-care identification is repeatedlyexecuted under condition that each bit of frequent scan vectors is fixed to binary values (0 or 1).Besides, a code extension technique is adopted for improving compression efficiency with keepingdecompressor circuits simple in the manner that the code length for infrequent scan vectors isdesigned as double of that for frequent ones. The effectiveness of the proposed method is shownthrough experiments for ISCAS'89 and ITC'99 benchmark circuits.展开更多
The power and area optimization of Reed-Muller （RM） circuits has been widely concerned. However, almost none of the exiting power and area optimization approaches can obtain all the Pareto optimal solutions of the o...The power and area optimization of Reed-Muller （RM） circuits has been widely concerned. However, almost none of the exiting power and area optimization approaches can obtain all the Pareto optimal solutions of the original problem and are efficient enough. Moreover, they have not considered the don＇t care terms, which makes the circuit performance unable to be further optimized. In this paper, we propose a power and area optimization approach of mixed polarity RM expression （MPRM） for incompletely specified Boolean functions based on Non-Dominated Sorting Genetic Algorithm II （NSGA-II）. Firstly, the incompletely specified Boolean function is transformed into zero polarity incompletely specified MPRM （ISMPRM） by using a novel ISMPRM acquisition algorithm. Secondly, the polarity and allocation of don＇t care terms of ISMPRM is encoded as chromosome. Lastly, the Pareto optimal solutions are obtained by using NSGA-II, in which MPRM corresponding to the given chromosome is obtained by using a chromosome conversion algorithm. The results on incompletely specified Boolean functions and MCNC benchmark circuits show that a significant power and area improvement can be made compared with the existing power and area optimization approaches of RM circuits.展开更多
基金This work was supported in part by the National Natural Science Foundation of China(NSFC)under Grant Nos.60576031,60633060,60606008,90607010,the National Grand Fundamental Research 973 Program of China under Grant Nos.2005CB321604 and 2005CB321605the Science Foundation of Hefei University of Technology under Grant Nos. 070501F and 060501F.Y.Han's work is also supported by the fund of Chinese Academy of Sciences due to the President Scholarship.
文摘It is a well-known fact that test power consumption may exceed that during functional operation. Leakage power dissipation caused by leakage current in Complementary Metal-Oxide-Semiconductor （CMOS） circuits during test has become a significant part of the total power dissipation. Hence, it is important to reduce leakage power to prolong battery life in portable systems which employ periodic self-test, to increase test reliability and to reduce test cost. This paper analyzes leakage current and presents a kind of leakage current simulator based on the transistor stacking effect. Using it, we propose techniques based on don＇t care bits （denoted by Xs） in test vectors to optimize leakage current in integrated circuit （IC） test by genetic algorithm. The techniques identify a set of don＇t care inputs in given test vectors and reassign specified logic values to the X inputs by the genetic algorithm to get minimum leakage vector （MLV）. Experimental results indicate that the techniques can effectually optimize leakage current of combinational circuits and sequential circuits during test while maintaining high fault coverage,
文摘This paper proposes an effective method for reducing test data volume undermultiple scan chain designs. The proposed method is based on reduction of distinct scan vectorsusing selective don't-care identification. Selective don't-care identification is repeatedlyexecuted under condition that each bit of frequent scan vectors is fixed to binary values (0 or 1).Besides, a code extension technique is adopted for improving compression efficiency with keepingdecompressor circuits simple in the manner that the code length for infrequent scan vectors isdesigned as double of that for frequent ones. The effectiveness of the proposed method is shownthrough experiments for ISCAS'89 and ITC'99 benchmark circuits.
基金This work is supported by the National Natural Science Foundation of China under Grant Nos. 60973106, 61370059, 61232009, and 81571142, Beijing Natural Science Foundation under Grant No. 4152030, the Fundamental Research Funds for the Central Universities of China under Grant Nos. YWF-15-CJSYS-085 and YWF-14-JSJXY-14, the Fund of the State Key Laboratory of Computer Architecture of China under Grant No. CARCH201507, the Open Project Program of National Engineering Research Center for Science and Technology Resources Sharing Service （Beihang University）, and the Fund of the State Key Laboratory of Software Development Environment of China under Grant No. SKLSDE-2016ZX-15.
文摘The power and area optimization of Reed-Muller （RM） circuits has been widely concerned. However, almost none of the exiting power and area optimization approaches can obtain all the Pareto optimal solutions of the original problem and are efficient enough. Moreover, they have not considered the don＇t care terms, which makes the circuit performance unable to be further optimized. In this paper, we propose a power and area optimization approach of mixed polarity RM expression （MPRM） for incompletely specified Boolean functions based on Non-Dominated Sorting Genetic Algorithm II （NSGA-II）. Firstly, the incompletely specified Boolean function is transformed into zero polarity incompletely specified MPRM （ISMPRM） by using a novel ISMPRM acquisition algorithm. Secondly, the polarity and allocation of don＇t care terms of ISMPRM is encoded as chromosome. Lastly, the Pareto optimal solutions are obtained by using NSGA-II, in which MPRM corresponding to the given chromosome is obtained by using a chromosome conversion algorithm. The results on incompletely specified Boolean functions and MCNC benchmark circuits show that a significant power and area improvement can be made compared with the existing power and area optimization approaches of RM circuits.
