A new high voltage SOI LDMOS with triple RESURF structure

A novel triple RESURF（T-resurf） SOI LDMOS structure is proposed.This structure has a P-type buried layer.Firstly,the depletion layer can extend on both sides of the P-buried layer,serving as a triple RESURF and leading to a high drift doping and a low on-resistance.Secondly,at a high doping concentration of the drift region, the P-layer can reduce high bulk electric field in the drift region and enhance the vertical electric field at the drain side,which results in uniform bulk electric field distributions and an enhanced BV.The proposed structure is used in SOI devices for the first time.The T-resurf SOI LDMOS with BV = 315 V is obtained by simulation on a 6μm-thick SOI layer over a 2μm-thick buried oxide layer,and its R_（sp） is reduced from 16.5 to 13.8 mΩ·cm^2 in comparison with the double RESURF（D-resurf） SOI LDMOS.When the thickness of the SOI layer increases, T-resurf SOI LDMOS displays a more obvious effect on the enhancement of BV^2/R_（on）.It reduces R_（sp） by 25%in 400 V SOI LDMOS and by 38%in 550 V SOI LDMOS compared with the D-resurf structure.

Novel SOI double-gate MOSFET with a P-type buried layer

An ultra-low specific on-resistance（R_（on,sp）） integrated silicon-on-insulator（SOI） double-gate triple RESURF（reduced surface field） n-type MOSFET（DG T-RESURF） is proposed.The MOSFET features two structures： an integrated double gates structure（DG） that combines a planar gate with an extended trench gate,and a p-type buried layer（BP） in the n-type drift region.First,the DG forms dual conduction channels and shortens the forward current path,so reducing R_（on,sp）.The DG works as a vertical field plate to improve the breakdown voltage （BV） characteristics.Second,the BP forms a triple RESURF structure（T-RESURF）,which not only increases the drift doping concentration but also modulates the electric field.This results in a reduced R_（on,sp） and an improved BV.Third,the extended trench gate and the BP linked with the p-body region reduce the sensitivity of the BV to position of the BP.The BV of 325 V and R_（on,sp） of 8.6 mΩ·cm^2 are obtained for the DG T-RESURF by simulation. R_（on,sp） of DG T-RESURF is decreased by 63.4%in comparison with a planar-gate single RESURF MOSFET（PG S-RESURF）,and the BV is increased by 9.8%.

A 700 V BCD technology platform for high voltage applications

A 700 V BCD technology platform is presented for high voltage applications. An important feature is that all the devices have been realized by using a fully implanted technology in a p-type single crystal without an epitaxial or a buried layer. An economical manufacturing process, requiring only 10 masking steps, yields a broad range of MOS and bipolar components integrated on a common substrate, including 700 V nLDMOS, 200 V nLDMOS, 80 V nLDMOS, 60 V nLDMOS, 40 V nLDMOS, 700 V nJFET, and low voltage devices. A robust double RESURF nLDMOS with a breakdown voltage of 800 V and specific on-resistance of 206.2 mf2.cm2 is successfully optimized and realized. The results of this technology are low fabrication cost, simple process and small chip area for PIC products.