A Microwave High Power Static Induction Transistor with Double Dielectrics Gate Structure

The designing approaches and key fabricating technologies for high frequency high power double dielectrics gate static induction transistor (DDG SIT) with mixed non-saturating I-V characteristics are presented.The effects of parasitic gate-source capacitance (C gs) on the power performance of SIT are discussed.The main methods and considerations to diminish C gs,consequently to improve the high power performance are given.Synchronous epitaxy technology is the critical step to decrease C gs.The 7-μm pitch DDG SIT delivering output power >20W with >7dB power gain and >70% drain efficiency at 400MHz,and delivering output power >7W with >5dB power gain and >50% drain efficiency at 700MHz are successfully fabricated.

Structure Design Considerations of a Sub-50nm Self-Aligned Double-Gate MOSFET

A comprehensive way to design a sub 50nm SADG MOSFET with the ability of being fabricated by improved CMOS technique is described.Under this way,the gate length and thickness of Si island of DG device show many different scaling limits for various elements.Meanwhile,the spacer insulator shows a kind of width thickness on device drain current and circuit speed.A model about that effect is developed and offers design consideration for future.A new design of channel doping profile,called SCD,is also discussed here in detail.The DG device with SCD can achieve a good balance between the volume inversion operation mode and the control of V th .Finally,a guideline to make a SADG MOSFET is presented.

Peculiar Nonlinear Depletion in Double-Layered Gated Si-δ-Doped GaAs

The low-temperature measurement of Hall effect of the two-dimensional electron system in a double-layered gated Si-δ-doped GaAs is presented.A complex peculiar nonlinear dependence of the depletion on gate voltage is observed.The nonlinearity is also explained on the basis of the assumption that the double-capacity model consists of two δ-doped two-dimensional electron layers and a metallic gate,and the experimental result that the electron mobility is linear with the electron density on a log-log scale.

Investigation of the surface orientation influence on 10-nm double gate GaSb nMOSFETs

The performance of double gate GaSb nMOSFETs with surface orientations of（100） and（111） are compared by deterministically solving the time-dependent Boltzmann transport equation（BTE）.Results show that the on-state current of the device with（111） surface orientation is almost three times larger than the（100） case due to the higher injection velocity.Moreover,the scattering rate of the（111） device is slightly lower than that of the（100） device.

Wavelength-dependence of double optical gating for attosecond pulse generation

Both polarization gating （PG） and double optical gating （DOG） are productive methods to generate single attosecond （as） pulses. In this paper, considering the ground-state depletion effect, we investigate the wavelength-dependence of the DOG method in order to optimize the generation of single attosecond pulses for the future application. By calculating the ionization probabilities of the leading edge of the pulse at different driving laser wavelengths, we obtain the upper limit of duration for the driving laser pulse for the DOG setup. We find that the upper limit duration increases with the increase of laser wavelength. We further describe the technical method of choosing and calculating the thickness values of optical components for the DOG setup.

MEEMD-DBA-based short term traffic flow prediction

Aiming at the problem that ensemble empirical mode decomposition(EEMD)method can not completely neutralize the added noise in the decomposition process,which leads to poor reconstruction of decomposition results and low accuracy of traffic flow prediction,a traffic flow prediction model based on modified ensemble empirical mode decomposition(MEEMD),double-layer bidirectional long-short term memory(DBiLSTM)and attention mechanism is proposed.Firstly,the intrinsic mode functions(IMFs)and residual components(Res)are obtained by using MEEMD algorithm to decompose the original traffic data and separate the noise in the data.Secondly,the IMFs and Res are put into the DBiLSTM network for training.Finally,the attention mechanism is used to enhance the extraction of data features,then the obtained results are reconstructed and added.The experimental results show that in different scenarios,the MEEMD-DBiLSTM-attention(MEEMD-DBA)model can reduce the data reconstruction error effectively and improve the accuracy of the short-term traffic flow prediction.

A Radiation Hardened Power Device——VDMNOSFET

A radiation hardened N channel Si power device——VDMNOSFET (Vertical Double Diffused Metal Nitride Oxide Semiconductor Field Effect Transistor) is fabricated by using a double layer (Si 3N 4 SiO 2) gate dielectric and a self aligned heavily doped shallow P + region.The effects of ionizing radiation and transient high dose rate radiation of the power VDMNOSFET are also presented.Good radiation hardening performance is obtained,compared with the conventional power VDMOSFET.For the specified 200V VDMNOSFET,the threshold voltage shifts is only -0 5V at a Gamma dose of 1Mrad(Si) with +10V gate bias;the transconductance is degraded by 10% at a Gamma dose of 1Mrad(Si);and no burnout failures occur at the transient high dose rate of 1×10 12 rad(Si)/s.It is demonstrated that the ionizing radiation tolerance and burnout susceptibilities of the power MOSFET are improved significantly by using a double layer (Si 3N 4 SiO 2) gate dielectric and a self aligned heavily doped shallow P + region.

A review on performance comparison of advanced MOSFET structures below 45 nm technology node

CMOS technology is one of the most frequently used technologies in the semiconductor industry as it can be successfully integrated with ICs.Every two years the number of MOS transistors doubles because the size of the MOSFET is reduced.Reducing the size of the MOSFET reduces the size of the channel length which causes short channel effects and it increases the leakage current.To reduce the short channel effects new designs and technologies are implemented.Double gate MOSFET design has shown improvement in performance as amplifiers over a single MOSFET.Silicon-based MOSFET design can be used in a harsh environment.It has been used in various applications such as in detecting biomolecules.The increase in number of gates increases the current drive capability of transistors.GAA MOSFET is an example of a quadruple gate around the four sides of channel that increases gate control over the channel region.It also increases effective channel width that improves drain current and reduces leakage current keeping short channel effects under limit.Junctionless MOSFET operates faster and uses less power with increase in ON-state current leading to a good value of ION/IOFF ratio.In this paper,several gate and channel engineered MOSFET structures are analyzed and compared for sub 45 nm technology node.A comparison among different MOSFET structures has been made for subthreshold performance parameters in terms of IOFF,subthreshold slope and DIBL values.The analog/RF performance is analyzed for transconductance,effective transistor capacitances,stability factor and critical frequency.The paper also covers different applications of advance MOSFET structures in analog/digital or IoT/biomedical applications.

A unified charge-based model for SOI MOSFETs applicable from intrinsic to heavily doped channel

A unified charge-based model for fully depleted silicon-on-insulator （SOI） metal oxide semiconductor field-effect transistors （MOSFETs） is presented. The proposed model is accurate and applicable from intrinsic to heavily doped channels with various structure parameters. The framework starts from the one-dimensional Poisson Boltzmann equa- tion, and based on the full depletion approximation, an accurate inversion charge density equation is obtained. With the inversion charge density solution, the unified drain current expression is derived, and a unified terminal charge and intrinsic capacitance model is also derived in the quasi-static case. The validity and accuracy of the presented analytic model is proved by numerical simulations.

DC and analog/RF performance of C-shaped pocket TFET(CSP-TFET)with fully overlapping gate

A C-shaped pocket tunnel field effect transistor(CSP-TFET)has been designed and optimized based on the traditional double-gate TFETs by introducing a C-shaped pocket region between the source and channel to improve the device performance.A gate-to-pocket overlapping structure is also examined in the proposed CSP-TFET to enhance the gate controllability.The effects of the pocket length,pocket doping concentration and gate-to-pocket overlapping structure on the DC and analog/RF characteristics of the CSP-TFET are estimated after calibrating the tunneling model in double-gate TFETs.The DC and analog/RF performance such as on-state current(Ion),on/off current ratio(Ion/Ioff),subthreshold swing(SS)transconductance(g;),cut-off frequency(f_(T))and gain-bandwidth product(GBP)are investigated.The optimized CSPTFET device exhibits excellent performance with high I_(off)(9.98×10^(-4)A/μm),high I_(on)/I_(off)(~10^(11)),as well as low SS(~12 m V/dec).The results reveal that the CSP-TFET device could be a potential alternative for the next generation of semiconductor devices.

Ultra-low specific on-resistance SOI double-gate trench-type MOSFET

An ultra-low specific on-resistance（R_（on,sp）） silicon-on-insulator（SOI） double-gate trench-type MOSFET （DG trench MOSFET） is proposed.The MOSFET features double gates and an oxide trench：the oxide trench is in the drift region,one trench gate is inset in the oxide trench and one trench gate is extended into the buried oxide.Firstly,the double gates reduce R_（on,sp） by forming dual conduction channels.Secondly,the oxide trench not only folds the drift region,but also modulates the electric field,thereby reducing device pitch and increasing the breakdown voltage（BV）.A BV of 93 V and a R_（on,sp） of 51.8 mΩ·mm^2 is obtained for a DG trench MOSFET with a 3μm half-cell pitch.Compared with a single-gate SOI MOSFET（SG MOSFET） and a single-gate SOI MOSFET with an oxide trench（SG trench MOSFET）,the R_（on,sp） of the DG trench MOSFET decreases by 63.3%and 33.8% at the same BV,respectively.

Novel SOI double-gate MOSFET with a P-type buried layer

An ultra-low specific on-resistance（R_（on,sp）） integrated silicon-on-insulator（SOI） double-gate triple RESURF（reduced surface field） n-type MOSFET（DG T-RESURF） is proposed.The MOSFET features two structures： an integrated double gates structure（DG） that combines a planar gate with an extended trench gate,and a p-type buried layer（BP） in the n-type drift region.First,the DG forms dual conduction channels and shortens the forward current path,so reducing R_（on,sp）.The DG works as a vertical field plate to improve the breakdown voltage （BV） characteristics.Second,the BP forms a triple RESURF structure（T-RESURF）,which not only increases the drift doping concentration but also modulates the electric field.This results in a reduced R_（on,sp） and an improved BV.Third,the extended trench gate and the BP linked with the p-body region reduce the sensitivity of the BV to position of the BP.The BV of 325 V and R_（on,sp） of 8.6 mΩ·cm^2 are obtained for the DG T-RESURF by simulation. R_（on,sp） of DG T-RESURF is decreased by 63.4%in comparison with a planar-gate single RESURF MOSFET（PG S-RESURF）,and the BV is increased by 9.8%.

Hetero-gate-dielectric double gate junctionless transistor(HGJLT)with reduced band-to-band tunnelling effects in subthreshold regime

We propose a hetero-gate-dielectric double gate junctionless transistor （HGJLT）, taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects ＆band-to-band tunnelling （BTBT） in the sub-threshold region. A junctionless transistor （JLT） is turned off by the depletion of carriers in the highly doped thin channel （device layer） which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel.These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor （n-p-n BJT for channel JLT） in the lateral direction by the source （emitter）, channel （base） and drain （collector） regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.

Novel vertical channel double gate structures for high density and low power flash memory applications

The flash memory technology meets physical and technical obstacles in further scaling. New structures and new materials are implemented as possible solutions. This paper focuses on two kinds of new flash cells for high density and low power memory applications based on the vertical channel double gate structure. The proposed VD-NROM with dual-nitride-trapping-layer and vertical structure can achieve four-bit-per-cell storage capability. And the proposed VSAS-FG cell benefits the high programming efficiency, low power and high density capability, which can be realized without any additional mask and can achieve the self-alignment of the split-gate channel and the floating-gate. The two novel flash cell structures can be considered as potential candidates for different flash memory applications.

The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor

The analog performance of gate misaligned dual material double gate junctionless transistor is demonstrated for the first time. The cases considered are where misalignment occurs towards source side and towards drain side. The analog performance parameters analyzed are： transconductance, output conductance, intrinsic gain and cut-off frequency. These figures of merits （FOMs） are compared with a dual material double gate inversion mode transistor under same gate misalignment condition. The impacts of different length of control gate （L 1） for a given gate length （L） are also studied and the optimum lengths La under misalignment condition to have better analog FOMs and high tolerance to misalignment are presented.

Effects of Unintended Dopants on I-V Characteristics of the Double-Gate MOSFETs,a Simulation Study

In this paper, we study the effects of an unintended dopant in the channel on the current-voltage char-acteristics of a Double-Gate (DG) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Non-Equilibrium Green's Function (NEGF) approach is used. A quantum transport model to calculate the drain current is presented and subthreshold swing and drain induced barrier lowering (DIBL) effect are studied.

Device and circuit analysis of a sub 20 nm double gate MOSFET with gate stack using a look-up-table-based approach

In this paper, we explore the possibility of mapping devices designed in TCAD environment to its modeled version developed in cadence virtuoso environment using a look-up table （LUT） approach. Circuit simu- lation of newly designed devices in TCAD environment is a very slow and tedious process involving complex scripting. Hence, the LUT based modeling approach has been proposed as a faster and easier alternative in ca- dence environment. The LUTs are prepared by extracting data from the device characteristics obtained from device simulation in TCAD. A comparative study is shown between the TCAD simulation and the LUT-based alternative to showcase the accuracy of modeled devices. Finally the look-up table approach is used to evaluate the perform- ance of circuits implemented using 14 nm nMOSFET.

Design and simulation of nanoscale double-gate TFET/tunnel CNTFET

A double-gate tunnel field-effect transistor （DG tunnel FET） has been designed and investigated for various channel materials such as silicon （Si）, gallium arsenide （GaAs）, alminium gallium arsenide （A1xGa1-xAs） and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator. The proposed devices are com- pared on the basis of inverse subthreshold slope （SS）, ION/IoFF current ratio and leakage current. Using Si as the channel material limits the property to reduce leakage current with scaling of channel, whereas the A1xGa1-xAs based DG tunnel FET provides a better ION/IOFF current ratio （2.51 × 10^6） as compared to other devices keeping the leakage current within permissible limits. The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down. The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time, which makes it suitable for memory based circuits.

Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOS- FET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO （Atlas） tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of syrnmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2.

A Finite Volume Method for the Multi Subband Boltzmann Equation with Realistic 2D Scattering in Double Gate MOSFETs

We propose a deterministic solver for the time-dependent multi-subband Boltzmann transport equation(MSBTE)for the two dimensional(2D)electron gas in double gate metal oxide semiconductor field effect transistors(MOSFETs)with flared out source/drain contacts.A realistic model with six-valleys of the conduction band of silicon and both intra-valley and inter-valley phonon-electron scattering is solved.We propose a second order finite volume method based on the positive and flux conservative(PFC)method to discretize the Boltzmann transport equations(BTEs).The transport part of the BTEs is split into two problems.One is a 1D transport problem in the position space,and the other is a 2D transport problem in the wavevector space.In order to reduce the splitting error,the 2D transport problem in the wavevector space is solved directly by using the PFC method instead of splitting into two 1D problems.The solver is applied to a nanoscale double gate MOSFET and the current-voltage characteristic is investigated.Comparison of the numerical results with ballistic solutions show that the scattering influence is not ignorable even when the size of a nanoscale semiconductor device goes to the scale of the electron mean free path.