Common Base Four-Finger InGaAs/InP Double Heterojunction Bipolar Transistor with Maximum Oscillation Frequency 535 GHz

A common base four-finger InOaAs/InP double heterojunction bipolar transistor with 535 OHz fmax by using the 0.5 μm emitter technology is fabricated. Multi-finger design is used to increase the input current. Common base configuration is compared with common emitter configuration, and shows a smaller K factor at high frequency span, indicating a larger breakpoint frequency of maximum stable gain/maximum available gain （MSG/MAG） and thus a higher gain near the cut-off frequency, which is useful in THz amplifier design.

A G-band terahertz monolithic integrated amplifier in 0.5-μm InP double heterojunction bipolar transistor technology

Design and characterization of a G-band（140–220 GHz） terahertz monolithic integrated circuit（TMIC） amplifier in eight-stage common-emitter topology are performed based on the 0.5-μm In Ga As/In P double heterojunction bipolar transistor（DHBT）. An inverted microstrip line is implemented to avoid a parasitic mode between the ground plane and the In P substrate. The on-wafer measurement results show that peak gains are 20 dB at 140 GHz and more than 15-dB gain at 140–190 GHz respectively. The saturation output powers are-2.688 dBm at 210 GHz and-2.88 dBm at 220 GHz,respectively. It is the first report on an amplifier operating at the G-band based on 0.5-μm InP DHBT technology. Compared with the hybrid integrated circuit of vacuum electronic devices, the monolithic integrated circuit has the advantage of reliability and consistency. This TMIC demonstrates the feasibility of the 0.5-μm InGaAs/InP DHBT amplifier in G-band frequencies applications.

Physical modeling based on hydrodynamic simulation for the design of InGaAs/InP double heterojunction bipolar transistors

A physical model for scaling and optimizing InGaAs/InP double heterojunction bipolar transistors（DHBTs） based on hydrodynamic simulation is developed.The model is based on the hydrodynamic equation,which can accurately describe non-equilibrium conditions such as quasi-ballistic transport in the thin base and the velocity overshoot effect in the depleted collector.In addition,the model accounts for several physical effects such as bandgap narrowing,variable effective mass,and doping-dependent mobility at high fields.Good agreement between the measured and simulated values of cutoff frequency,f t,and maximum oscillation frequency,f max,are achieved for lateral and vertical device scalings.It is shown that the model in this paper is appropriate for downscaling and designing InGaAs/InP DHBTs.

High breakdown voltage InGaAs/InP double heterojunction bipolar transistors with f_(max)=256 GHz and BV_(CEO)= 8.3 V

An InGaAs/InP DHBT with an InGaAsP composite collector is designed and fabricated using triple mesa structural and planarization technology. All processes are on 3-inch wafers. The DHBT with an emitter area of 1×15 μm2 exhibits a current cutoff frequency ft = 170 GHz and a maximum oscillation frequency fmax = 256 GHz. The breakdown voltage is 8.3 V, which is to our knowledge the highest BVcEo ever reported for InGaAs/InP DHBTs in China with comparable high frequency performances. The high speed InGaAs/InP DHBTs with high breakdown voltage are promising for voltage-controlled oscillator and mixer applications at W band or even higher frequencies.

Frequency stability of InP HBT over 0.2 to 220 GHz

The frequency stabilities of lnP DHBTs in a broadband over 1 to 220 GHz are investigated. A hybrid π-topology small-signal model is used to accurately capture the parasitics of devices. The model parameters are extracted from measurements analytically. The investigation results show that the excellent agreement between the measured and simulated data is obtained in the frequency range 200 MHz to 220 GHz. The dominant parameters of the π-topology model, bias conditions and emitter area have significant effects on the stability factor K. The HBT model can be unconditionally stable by reasonable selection of the proper bias condition and the physical layout of the device.