A continuous analytic channel potential solution to doped symmetric double-gate MOSFETs from the accumulation to the strong-inversion region

A continuous yet analytic channel potential solution is proposed for doped symmetric double-gate （DG） MOSFETs from the accumulation to the strong-inversion region. Analytical channel potential relationship is derived from the complete 1-D Poisson equation physically, and the channel potential solution of the DG MOSFET is obtained analytically. The extensive comparisons between the presented solution and the numerical simulation illustrate that the solution is not only accurate and continuous in the whole operation regime of DG MOSFETs, but also valid to wide doping concentration and various geometrical sizes, without employing any fitting parameter.

Improved double-gate armchair silicene nanoribbon field-effect-transistor at large transport bandgap

The electrical characteristics of a double-gate armchair silicene nanoribbon field-effect-transistor （DG ASiNR FET） are thoroughly investigated by using a ballistic quantum transport model based on non-equilibrium Green＇s function （NEGF） approach self-consistently coupled with a three-dimensional （3D） Poisson equation. We evaluate the influence of variation in uniaxial tensile strain, ribbon temperature and oxide thickness on the on-off current ratio, subthreshold swing, transconductance and the delay time of a 12-nm-length ultranarrow ASiNR FET. A novel two-parameter strain mag- nitude and temperature-dependent model is presented for designing an optimized device possessing balanced amelioration of all the electrical parameters. We demonstrate that employing HfO2 as the gate insulator can be a favorable choice and simultaneous use of it with proper combination of temperature and strain magnitude can achieve better device performance. Furthermore, a general model power （GMP） is derived which explicitly provides the electron effective mass as a function of the bandgap of a hydrogen passivated ASiNR under strain.

An improvement to computational efficiency of the drain current model for double-gate MOSFET

As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET. Time efficiency is one of the most important requirements for device modeling. In this paper, an improvement to the computational efficiency of the drain current model for double-gate MOSFETs is extended, and different calculation methods are compared and discussed. The results show that the calculation speed of the improved model is substantially enhanced. A two-dimensional device simulation is performed to verify the improved model. Furthermore, the model is implemented into the HSPICE circuit simulator in Verilog-A for practical application.

A compact two-dimensional analytical model of the electrical characteristics of a triple-material double-gate tunneling FET structure

This paper presents a compact two-dimensional analytical device model of surface potential,in addition to electric field of triple-material double-gate(TMDG)tunnel FET.The TMDG TFET device model is developed using a parabolic approximation method in the channel depletion space and a boundary state of affairs across the drain and source.The TMDG TFET device is used to analyze the electrical performance of the TMDG structure in terms of changes in potential voltage,lateral and vertical electric field.Because the TMDG TFET has a simple compact structure,the surface potential is computationally efficient and,therefore,may be utilized to analyze and characterize the gate-controlled devices.Furthermore,using Kane's model,the current across the drain can be modeled.The graph results achieved from this device model are close to the data collected from the technology computer aided design(TCAD)simulation.

Two-dimensional analytical models for asymmetric fully depleted double-gate strained silicon MOSFETs

This paper develops the simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET. The models mainly include the analytical equations of the surface potential, surface electric field and threshold voltage, which are derived by solving two dimensional Poisson equation in strained-Si layer. The models are verified by numerical simulation. Besides offering the physical insight into device physics in the model, the new structure also provides the basic designing guidance for further immunity of short channel effect and draininduced barrier-lowering of CMOS-based devices in nanometre scale.

Two-dimensional models of threshold voltage and subthreshold current for symmetrical double-material double-gate strained Si MOSFETs

The two-dimensional models for symmetrical double-material double-gate （DM-DG） strained Si （s-Si） metal-oxide semiconductor field effect transistors （MOSFETs） are presented. The surface potential and the surface electric field ex- pressions have been obtained by solving Poisson＇s equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate （SM-DG） MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.

A novel 10-nm physical gate length double-gate junction field effect transistor

A novel double-gate （DG） junction field effect transistor （JFET） with depletion operation mode is proposed in this paper. Compared with the conventional DG MOSFET, the novel DG JFET can achieve excellent performance with square body design, which relaxes the requirement on silicon film thickness of DG devices. Moreover, due to the structural symmetry, both p-type and n-type devices can be realized on exactly the same structure, which greatly simplifies integration. It can reduce the delay by about 60% in comparison with the conventional DG MOSFETs.

Performance of Double-Pole Four-Throw Double-Gate RF CMOS Switch in 45-nm Technology

In this paper, we have investigated the design parameters of RF CMOS switch, which will be used for the wireless tele-communication systems. A double-pole four-throw double-gate radio-frequency complementary-metal-oxide-semicon- ductor (DP4T DG RF CMOS) switch for operating at the 1 GHz is implemented with 45-nm CMOS process technology. This proposed RF switch is capable to select the data streams from the two antennas for both the transmitting and receiving processes. For the development of this DP4T DG RF CMOS switch we have explored the basic concept of the proposed switch circuit elements required for the radio frequency systems such as drain current, threshold voltage, resonant frequency, return loss, transmission loss, VSWR, resistances, capacitances, and switching speed.

Capacitive Model and S-Parameters of Double-Pole Four-Throw Double-Gate RF CMOS Switch

In this paper, we have analyzed the Double-Pole Four-Throw Double-Gate Radio-Frequency Complementary Metal-Oxide-Semiconductor (DP4T DG RF CMOS) switch using S-parameters for 1 GHz to 60 GHz of frequency range. DP4T DG RF CMOS switch for operation at high frequency is also analyzed with its capacitive model. The re-sults for the development of this proposed switch include the basics of the circuit elements in terms of capacitance, re-sistance, impedance, admittance, series equivalent and parallel equivalent of this network at different frequencies which are present in this switch whatever they are ON or OFF.

Analytical modeling of drain current and RF performance for double-gate fully depleted nanoscale SOI MOSFETs

A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs.Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI MOSFETs is also carried out.Finally this work is concluded by modeling the cut-off frequency, which is one of the main figures of merit for analog/RF performance for double-gate fully depleted nanoscale SOI MOSFETs.The results of the modeling are compared with those obtained by a 2D ATLAS device simulator to verify the accuracy of the proposed model.

Simulation study on short channel double-gate junctionless field-effect transistors

We study the characteristics of short channel double-gate(DG) junctionless(JL) FETs by device simulation. OutputⅠ-Ⅴcharacteristic degradations such as an extremely reduced channel length induced subthreshold slope increase and the threshold voltage shift due to variations of body doping and channel length have been systematically analyzed.Distributions of electron concentration,electric field and potential in the body channel region are also analyzed.Comparisons with conventional inversion-mode(IM) FETs,which can demonstrate the advantages of JL FETs,have also been performed.

A 2-D semi-analytical model of double-gate tunnel field-effect transistor

A 2-D semi-analytical model of double gate （DG） tunneling field-effect transistor （TFET） is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poisson equation is solved by using a semi-analytical method combined with an eigenfunction expansion method. The expression of the surface potential is obtained, which is a special function for the infinite series expressions. The influence of the mobile charges on the potential profile is taken into account in the proposed model. On the basis of the potential profile, the shortest tunneling length and the average electrical field can be derived, and the drain current is then constructed by using Kane＇s model. In particular, the changes of the tunneling parameters Ak and Bk influenced by the drain-source voltage are also incorporated in the predicted model. The proposed model shows a good agreement with TCAD simulation results under different drain-source voltages, silicon film thicknesses, gate dielectric layer thicknesses, and gate dielectric layer constants. Therefore, it is useful to optimize the DG TFET and this provides a physical insight for circuit level design.

A two-dimensional analytical model of fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs

On the basis of the exact resultant solution of two dimensional Poisson’s equations,a new accurate two-dimensional analytical model comprising surface channel potentials,a surface channel electric field and a threshold voltage for fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs is successfully developed. The model shows its validity by good agreement with the simulated results from a two-dimensional numerical simulator.Besides offering a physical insight into device physics,the model provides basic design guidance for fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs.

Modeling of subthreshold characteristics for undoped and doped deep nanoscale short channel double-gate MOSFETs

A model of subthreshold characteristics for both undoped and doped double-gate （DG） MOSFETs has been proposed. The models were developed based on solution of 2-D Poisson＇s equation using variable separa- tion technique. Without any fitting parameters, our proposed models can exactly reflect the degraded subthreshold characteristics due to nanoscale channel length. Also, design parameters such as body thickness, gate oxide thick- ness and body doping concentrations can be directly reflected from our models. The models have been verified by comparing with device simulations＇ results and found very good agreement.

Characteristics of vertical double-gate dual-strained-channel MOSFETs

A novel device structure with a vertical double-gate and dual-strained channel is presented.The electrical characteristics of this device with a gate length of 100 nm are simulated.With a Ge content of 20%,the drain currents of the strained-Si NMOSFET and the strained-SiGe PMOSFET compared to the universal SOI MOSFETs are enhanced by 26% and 33%,respectively;the risetime and the falltime of the strained-channel CMOS are greatly decreased by 50% and 25.47% compared to their traditional Si channel counterparts.The simulation results show that the vertical double-gate（DG） dual-strained-channel MOSFETs exhibit better drive capability,a higher transconductance,and a faster circuit speed for CMOS compared to conventional-Si MOSFETs.The new structure can be achieved by today＇s semiconductor manufacturing level.

Explicit solution of channel potential and drain current model in symmetric double-gate polysilicon TFTs

A physical and explicit surface potential model for undoped symmetric double-gate polysilicon thinfilm transistors has been derived based on an effective charge density approach of Poisson＇s equation with both exponential deep and tail state terms included. The proposed surface potential calculation is single-piece and eliminatestheregionalapproach.Modelpredictionsarecomparedtonumericalsimulationswithcloseagreement,having absolute error in the millivolt range. Furthermore, expressions of the drain current are given for a wide range of operation regions, which have been justified by thorough comparisons with experimental data.

Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers

A two-dimensional analytical model of double-gate（DG） tunneling field-effect transistors（TFETs） with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potential profile is also taken into account in order to improve the accuracy of the models. On the basis of potential profile,the electric field is derived and the expression for the drain current is obtained by integrating the BTBT generation rate. The model can be used to study the impact of interface trapped charges on the surface potential, the shortest tunneling length, the drain current and the threshold voltage for varying interface trapped charge densities, length of damaged region as well as the structural parameters of the DG TFET and can also be utilized to design the charge trapped memory devices based on TFET. The biggest advantage of this model is that it is more accurate,and in its expression there are no fitting parameters with small calculating amount. Very good agreements for both the potential, drain current and threshold voltage are observed between the model calculations and the simulated results.

Study on two-dimensional analytical models for symmetrical gate stack dual gate strained silicon MOSFETs

Based on the exact resultant solution of two-dimensional Poisson＇s equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor （CMOS）-based device in a nanoscale regime.

Two dimensional analytical model for a negative capacitance double gate tunnel field effect transistor with ferroelectric gate dielectric

Analytical models are presented for a negative capacitance double-gate tunnel field-effect transistor（NC DG TFET） with a ferroelectric gate dielectric in this paper. The model accurately calculates the channel potential profile by solving the Poisson equation with the Landau-Khalatnikov（LK） equation. Moreover, the effects of the channel mobile charges on the potential are also taken into account. We also analyze the dependences of the channel potential and the on-state current on the device parameters by changing the thickness of ferroelectric layer,ferroelectric material and also verify the simulation results accord with commercial TCAD. The results show that the device can obtain better characteristics when the thickness of the ferroelectric layer is larger as it can reduce the shortest tunneling length.