A continuous analytic channel potential solution to doped symmetric double-gate MOSFETs from the accumulation to the strong-inversion region

A continuous yet analytic channel potential solution is proposed for doped symmetric double-gate （DG） MOSFETs from the accumulation to the strong-inversion region. Analytical channel potential relationship is derived from the complete 1-D Poisson equation physically, and the channel potential solution of the DG MOSFET is obtained analytically. The extensive comparisons between the presented solution and the numerical simulation illustrate that the solution is not only accurate and continuous in the whole operation regime of DG MOSFETs, but also valid to wide doping concentration and various geometrical sizes, without employing any fitting parameter.

Analytical Modeling of Threshold Voltage for Double-Gate MOSFET Fully Comprising Quantum Mechanical Effects

The analytical solutions to 1D Schrdinger equation (in depth direction) in double gate (DG) MOSFETs are derived to calculate electron density and threshold voltage.The non uniform potential in the channel is concerned with an arbitrary depth so that the analytical solutions agree well with numerical ones.Then,an implicit expression for electron density and a closed form of threshold voltage are presented fully comprising quantum mechanical (QM) effects.This model predicts an increased electron density with an increasing channel depth in subthreshold region or mild inversion region.However,it becomes independent on channel depth in strong inversion region,which is in accordance with numerical analysis.It is also concluded that the QM model,which barely considers a box like potential in the channel,slightly over predicts threshold voltage and underestimates electron density,and the error increases with an increasing channel depth or a decreasing gate oxide thickness.

An improvement to computational efficiency of the drain current model for double-gate MOSFET

As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET. Time efficiency is one of the most important requirements for device modeling. In this paper, an improvement to the computational efficiency of the drain current model for double-gate MOSFETs is extended, and different calculation methods are compared and discussed. The results show that the calculation speed of the improved model is substantially enhanced. A two-dimensional device simulation is performed to verify the improved model. Furthermore, the model is implemented into the HSPICE circuit simulator in Verilog-A for practical application.

Two-dimensional analytical models for asymmetric fully depleted double-gate strained silicon MOSFETs

This paper develops the simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET. The models mainly include the analytical equations of the surface potential, surface electric field and threshold voltage, which are derived by solving two dimensional Poisson equation in strained-Si layer. The models are verified by numerical simulation. Besides offering the physical insight into device physics in the model, the new structure also provides the basic designing guidance for further immunity of short channel effect and draininduced barrier-lowering of CMOS-based devices in nanometre scale.

Two-dimensional models of threshold voltage and subthreshold current for symmetrical double-material double-gate strained Si MOSFETs

The two-dimensional models for symmetrical double-material double-gate （DM-DG） strained Si （s-Si） metal-oxide semiconductor field effect transistors （MOSFETs） are presented. The surface potential and the surface electric field ex- pressions have been obtained by solving Poisson＇s equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate （SM-DG） MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.

考虑源漏隧穿的DG MOSFET弹道输运及其模拟

在经典弹道输运模型中引入源漏隧穿 (S/ D tunneling) ,采用 WKB方法计算载流子源漏隧穿几率 ,对薄硅层(硅层厚度为 1nm) DG(dual gate) MOSFETs的器件特性进行了模拟 .模拟结果表明当沟道长度为 10 nm时 ,源漏隧穿电流在关态电流中占 2 5 % ,在开态电流中占 5 % .随着沟道长度进一步减小 ,源漏隧穿比例进一步增大 .因此 ,模拟必须包括源漏隧穿 .

Compact Modeling for Inversion Charge in Nanoscale DG-MOSFETs

A compact model for the integrated inversion charge density Qi in double-gate （DG-） MOSFETs is developed. For nanoscale applications,quantum confinement of the inversion carriers must be taken into account. Based on the previous work of Ge, we establish an expression for the surface potential with respect to Qi, and form an implicit equation, from which Qi can be solved. Results predicted by our model are compared to published data as well as results from Schred,a popular 1D numerical solver that solves the Poisson＇s and Schr6dinger equa- tions self-consistently. Good agreement is obtained for a wide range of silicon layer thickness,confirming the supe- riority of this model over previous work in this field.

A two-dimensional analytical modeling for channel potential and threshold voltage of short channel triple material symmetrical gate Stack(TMGS) DG-MOSFET

In the present work, a two-dimensional（2D） analytical framework of triple material symmetrical gate stack（TMGS）DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS;device simulator to affirm and formalize the proposed device structure.

A novel 10-nm physical gate length double-gate junction field effect transistor

A novel double-gate （DG） junction field effect transistor （JFET） with depletion operation mode is proposed in this paper. Compared with the conventional DG MOSFET, the novel DG JFET can achieve excellent performance with square body design, which relaxes the requirement on silicon film thickness of DG devices. Moreover, due to the structural symmetry, both p-type and n-type devices can be realized on exactly the same structure, which greatly simplifies integration. It can reduce the delay by about 60% in comparison with the conventional DG MOSFETs.

Performance of Double-Pole Four-Throw Double-Gate RF CMOS Switch in 45-nm Technology

In this paper, we have investigated the design parameters of RF CMOS switch, which will be used for the wireless tele-communication systems. A double-pole four-throw double-gate radio-frequency complementary-metal-oxide-semicon- ductor (DP4T DG RF CMOS) switch for operating at the 1 GHz is implemented with 45-nm CMOS process technology. This proposed RF switch is capable to select the data streams from the two antennas for both the transmitting and receiving processes. For the development of this DP4T DG RF CMOS switch we have explored the basic concept of the proposed switch circuit elements required for the radio frequency systems such as drain current, threshold voltage, resonant frequency, return loss, transmission loss, VSWR, resistances, capacitances, and switching speed.

Novel attributes and design considerations of effective oxide thickness in nano DG MOSFETs

Impacts of effective oxide thickness on a symmetric double-gate MOSFET with 9-nm gate length are studied, using full quantum simulation. The simulations are based on a self-consistent solution of the two-dimensional （2D） Poisson equation and the Schr6dinger equation within the non-equilibrium Green＇s function formalism. Oxide thickness and gate dielectric are investigated in terms of drain current, on-off current ratio, off current, sub-threshold swing, drain induced barrier lowering, transconductance, drain conductance, and voltage. Simulation results illustrate that we can improve the device performance by proper selection of the effective oxide thickness.

Capacitive Model and S-Parameters of Double-Pole Four-Throw Double-Gate RF CMOS Switch

In this paper, we have analyzed the Double-Pole Four-Throw Double-Gate Radio-Frequency Complementary Metal-Oxide-Semiconductor (DP4T DG RF CMOS) switch using S-parameters for 1 GHz to 60 GHz of frequency range. DP4T DG RF CMOS switch for operation at high frequency is also analyzed with its capacitive model. The re-sults for the development of this proposed switch include the basics of the circuit elements in terms of capacitance, re-sistance, impedance, admittance, series equivalent and parallel equivalent of this network at different frequencies which are present in this switch whatever they are ON or OFF.

Physical Parameter Variation Analysis on the Performance Characteristics of Nano DG-MOSFETs

DG-MOSFETs are the most widely explored device architectures for nano-scale CMOS circuit design in sub-50 nm due to the improved subthreshold slope and the reduced leakage power compared to bulk MOSFETs. In thin-film (tsi < 10 nm) DG-MOS structures, charge carriers are affected by tsi- induced quantum confinement along with the confinement caused by a very high electric field at the interface. Therefore, quantum confinement effects on the device characteristics are also quite important and it needs to be incorporated along with short channel effects for nano-scale circuit design. In this paper, we analyzed a DG-MOSFET structure at the 20 nm technology node incorporating quantum confinement effects and various short channel effects. The effect of physical parameter variations on performance characteristics of the device such as threshold voltage, subthreshold slope, ION - IOFF ratio, DIBL, etc. has been investigated and plotted through extensive TCAD simulations. The physical parameters considered in this paper are operating temperature (Top), channel doping concentration (Nc), gate oxide thickness (tox) and Silicon film thickness (tsi). It was observed that quantum confinement of charge carriers significantly affected the performance characteristics (mostly the subthreshold characteristics) of the device and therefore, it cannot be ignored in the subthreshold region-based circuit design like in many previous research works. The ATLASTM device simulator has been used in this paper to perform simulation and parameter extraction. The TCAD analysis presented in the manuscript can be incorporated for device modeling and device matching. It can be used to illustrate exact device behavior and for proper device control.

纳米级MOSFET多晶区量子修正解析模型

利用ISE8.0的DESSIS,对多晶区量子力学效应进行了摸拟。结果表明,纳米级MOSFET多晶区内的量子效应不可忽略,且它对器件特性的影响与多晶耗尽效应相反。从密度梯度模型,简化得到多晶区量子效应修正,并建立了多晶区内量子效应的集约模型。该模型与数值模拟结果吻合。

短沟道双栅MOSFET二维表面势解析模型

采用分解电势的方法求解二维泊松方程,建立了考虑电子准费米势的短沟道双栅MOSFET的二维表面势模型,并在其基础上导出了阈值电压、短沟道致阈值电压下降效应和漏极感应势垒降低效应的解析模型。研究了不同沟道长度、栅压和漏压情况下的沟道表面势,分析了沟道长度和硅膜厚度对短沟道效应的影响。研究结果表明,电子准费米势对开启后的器件漏端附近表面势有显著影响,新模型可弥补现有模型中漏端附近表面势误差较大的缺点;对于短沟道双栅MOSFET,适当减小硅膜厚度可抑制短沟道效应。

双栅掺杂隔离肖特基MOSFET的解析模型

通过考虑肖特基势垒降低效应求解三段连续的二维泊松方程,建立了双栅掺杂隔离肖特基MOSFET亚阈值区全沟道连续的电势模型。在该电势模型的基础上,推导了阈值电压模型和漏致势垒降低效应的表达式;研究了掺杂隔离区域不同掺杂浓度下的沟道电势分布,分析了沟道长度和厚度对短沟道效应的影响。结果表明,掺杂隔离区域能改善肖特基MOSFET的电学特性;对于短沟道双栅掺杂隔离肖特基MOSFET,适当减小沟道宽度能有效抑制短沟道效应。

On-current modeling of short-channel double-gate(DG) MOSFETs with a vertical Gaussian-like doping profile

An analytic drain current model is presented for doped short-channel double-gate MOSFETs with a Gaussian-like doping profile in the vertical direction of the channel. The present model is valid in linear and satura- tion regions of device operation. The drain current variation with various device parameters has been demonstrated. The model is made more physical by incorporating the channel length modulation effect. Parameters like transcon- ductance and drain conductance that are important in assessing the analog performance of the device have also been formulated. The model results are validated by numerical simulation results obtained by using the commercially available ATLAS^TM, a two dimensional device simulator from SILVACO.

Study on two-dimensional analytical models for symmetrical gate stack dual gate strained silicon MOSFETs

Based on the exact resultant solution of two-dimensional Poisson＇s equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor （CMOS）-based device in a nanoscale regime.

高k栅介质对短沟道双栅极MOSFET性能的影响

不断缩小半导体器件尺寸将引起二氧化硅绝缘层厚度逐渐地减薄,从而导致从栅极泄漏到衬底的栅极漏电流的明显增加,这制约了MOSFET性能的提升.为了进一步了解采用高k电介质材料增强MOSFET性能的物理机制,本文通过采用基于非平衡格林函数的数值模拟方法,探讨了高k电介质材料及其等效厚度对于短沟道双栅极MOSFET性能的影响.模拟结果表明,高k材料介电常数的增加或等效氧化层厚度(EOT)的减小均将引起沟道区域能量势垒高度的减小,从而导致沟道电子数密度的增加而使漏极电流增加.因此,采用高k电介质材料为绝缘膜可有效地束缚栅极漏电流,从而提高短沟道双栅极MOSFET的性能.

A Complete Surface Potential-Based Core Model for Undoped Symmetric Double-Gate MOSFETs

A surface potential-based model for undoped symmetric double-gate MOSFETs is derived by solving Poisson＇s equation to obtain the relationship between the surface potential and voltage in the channel region in a self-consistent way. The drain current expression is then obtained from Pao-Sah＇s double integral. The model consists of one set of surface potential equations,and the analytic drain current can be evaluated from the surface potential at the source and drain ends. It is demonstrated that the model is valid for all operation regions of the double-gate MOSFETs and without any need for simplification （e. g., by using the charge sheet assumption） or auxiliary fitting functions. The model has been verified by extensive comparisons with 2D numerical simulation under different operation conditions with different geometries. The consistency between the model calculation and numerical simulation demonstrates the accuracy of the model.