A novel planar DGDT FDSOI nMOSFET is presented, and the operation mechanism is discussed. The device fabrication processes and characteristics are simulated with Tsuprem 4 and Medici. The back-gate n-well is formed by...A novel planar DGDT FDSOI nMOSFET is presented, and the operation mechanism is discussed. The device fabrication processes and characteristics are simulated with Tsuprem 4 and Medici. The back-gate n-well is formed by implantation of phosphorus at a dosage of 3 × 10^13 cm^-2 and an energy of 250keV and connected directly to a front-gate n^+ polysilicon. This method is completely compatible with the conventional bulk silicon process. Simulation results show that a DGDT FDSOI nMOSFET not only retains the advantages of a conventional FDSOI nMOSFET over a partially depleted (PD) SOI nMOSFET--that is the avoidance of anomalous subthreshold slope and kink effects but also shows a better drivability than a conventional FDSOI nMOSFET.展开更多
A quasi two-dimensional (2D) analytical model of a double-gate (DG) MOSFET with Schottky source/drain is developed based on the Poisson equation.The 2D potential distribution in the channel is calculated.An expres...A quasi two-dimensional (2D) analytical model of a double-gate (DG) MOSFET with Schottky source/drain is developed based on the Poisson equation.The 2D potential distribution in the channel is calculated.An expression for threshold voltage for a short-channel DG MOSFET with Schottky S/D is also presented by defining the turn-on condition.The results of the model are verified by the numerical simulator DESSIS-ISE.展开更多
A continuous yet analytic channel potential solution is proposed for doped symmetric double-gate (DG) MOSFETs from the accumulation to the strong-inversion region. Analytical channel potential relationship is derive...A continuous yet analytic channel potential solution is proposed for doped symmetric double-gate (DG) MOSFETs from the accumulation to the strong-inversion region. Analytical channel potential relationship is derived from the complete 1-D Poisson equation physically, and the channel potential solution of the DG MOSFET is obtained analytically. The extensive comparisons between the presented solution and the numerical simulation illustrate that the solution is not only accurate and continuous in the whole operation regime of DG MOSFETs, but also valid to wide doping concentration and various geometrical sizes, without employing any fitting parameter.展开更多
The electrical characteristics of a double-gate armchair silicene nanoribbon field-effect-transistor (DG ASiNR FET) are thoroughly investigated by using a ballistic quantum transport model based on non-equilibrium G...The electrical characteristics of a double-gate armchair silicene nanoribbon field-effect-transistor (DG ASiNR FET) are thoroughly investigated by using a ballistic quantum transport model based on non-equilibrium Green's function (NEGF) approach self-consistently coupled with a three-dimensional (3D) Poisson equation. We evaluate the influence of variation in uniaxial tensile strain, ribbon temperature and oxide thickness on the on-off current ratio, subthreshold swing, transconductance and the delay time of a 12-nm-length ultranarrow ASiNR FET. A novel two-parameter strain mag- nitude and temperature-dependent model is presented for designing an optimized device possessing balanced amelioration of all the electrical parameters. We demonstrate that employing HfO2 as the gate insulator can be a favorable choice and simultaneous use of it with proper combination of temperature and strain magnitude can achieve better device performance. Furthermore, a general model power (GMP) is derived which explicitly provides the electron effective mass as a function of the bandgap of a hydrogen passivated ASiNR under strain.展开更多
As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET. Time efficiency is one of the most important requirements for devic...As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET. Time efficiency is one of the most important requirements for device modeling. In this paper, an improvement to the computational efficiency of the drain current model for double-gate MOSFETs is extended, and different calculation methods are compared and discussed. The results show that the calculation speed of the improved model is substantially enhanced. A two-dimensional device simulation is performed to verify the improved model. Furthermore, the model is implemented into the HSPICE circuit simulator in Verilog-A for practical application.展开更多
This paper develops the simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET. The models mainly include the analytical equations of the surface potenti...This paper develops the simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET. The models mainly include the analytical equations of the surface potential, surface electric field and threshold voltage, which are derived by solving two dimensional Poisson equation in strained-Si layer. The models are verified by numerical simulation. Besides offering the physical insight into device physics in the model, the new structure also provides the basic designing guidance for further immunity of short channel effect and draininduced barrier-lowering of CMOS-based devices in nanometre scale.展开更多
This paper presents a compact two-dimensional analytical device model of surface potential,in addition to electric field of triple-material double-gate(TMDG)tunnel FET.The TMDG TFET device model is developed using a p...This paper presents a compact two-dimensional analytical device model of surface potential,in addition to electric field of triple-material double-gate(TMDG)tunnel FET.The TMDG TFET device model is developed using a parabolic approximation method in the channel depletion space and a boundary state of affairs across the drain and source.The TMDG TFET device is used to analyze the electrical performance of the TMDG structure in terms of changes in potential voltage,lateral and vertical electric field.Because the TMDG TFET has a simple compact structure,the surface potential is computationally efficient and,therefore,may be utilized to analyze and characterize the gate-controlled devices.Furthermore,using Kane's model,the current across the drain can be modeled.The graph results achieved from this device model are close to the data collected from the technology computer aided design(TCAD)simulation.展开更多
The two-dimensional models for symmetrical double-material double-gate (DM-DG) strained Si (s-Si) metal-oxide semiconductor field effect transistors (MOSFETs) are presented. The surface potential and the surface...The two-dimensional models for symmetrical double-material double-gate (DM-DG) strained Si (s-Si) metal-oxide semiconductor field effect transistors (MOSFETs) are presented. The surface potential and the surface electric field ex- pressions have been obtained by solving Poisson's equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate (SM-DG) MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.展开更多
A novel double-gate (DG) junction field effect transistor (JFET) with depletion operation mode is proposed in this paper. Compared with the conventional DG MOSFET, the novel DG JFET can achieve excellent performan...A novel double-gate (DG) junction field effect transistor (JFET) with depletion operation mode is proposed in this paper. Compared with the conventional DG MOSFET, the novel DG JFET can achieve excellent performance with square body design, which relaxes the requirement on silicon film thickness of DG devices. Moreover, due to the structural symmetry, both p-type and n-type devices can be realized on exactly the same structure, which greatly simplifies integration. It can reduce the delay by about 60% in comparison with the conventional DG MOSFETs.展开更多
In this paper, we have investigated the design parameters of RF CMOS switch, which will be used for the wireless tele-communication systems. A double-pole four-throw double-gate radio-frequency complementary-metal-oxi...In this paper, we have investigated the design parameters of RF CMOS switch, which will be used for the wireless tele-communication systems. A double-pole four-throw double-gate radio-frequency complementary-metal-oxide-semicon- ductor (DP4T DG RF CMOS) switch for operating at the 1 GHz is implemented with 45-nm CMOS process technology. This proposed RF switch is capable to select the data streams from the two antennas for both the transmitting and receiving processes. For the development of this DP4T DG RF CMOS switch we have explored the basic concept of the proposed switch circuit elements required for the radio frequency systems such as drain current, threshold voltage, resonant frequency, return loss, transmission loss, VSWR, resistances, capacitances, and switching speed.展开更多
In this paper, we have analyzed the Double-Pole Four-Throw Double-Gate Radio-Frequency Complementary Metal-Oxide-Semiconductor (DP4T DG RF CMOS) switch using S-parameters for 1 GHz to 60 GHz of frequency range. DP4T D...In this paper, we have analyzed the Double-Pole Four-Throw Double-Gate Radio-Frequency Complementary Metal-Oxide-Semiconductor (DP4T DG RF CMOS) switch using S-parameters for 1 GHz to 60 GHz of frequency range. DP4T DG RF CMOS switch for operation at high frequency is also analyzed with its capacitive model. The re-sults for the development of this proposed switch include the basics of the circuit elements in terms of capacitance, re-sistance, impedance, admittance, series equivalent and parallel equivalent of this network at different frequencies which are present in this switch whatever they are ON or OFF.展开更多
The previous report (XI) gave the electrochemical-potential theory of the Bipolar Field-Effect Transistors. This report (XII) gives the drift-diffusion theory. Both treat 1-gate and 2-gate, pure-base and impure-ba...The previous report (XI) gave the electrochemical-potential theory of the Bipolar Field-Effect Transistors. This report (XII) gives the drift-diffusion theory. Both treat 1-gate and 2-gate, pure-base and impure-base, and thin and thick base. Both utilize the surface and bulk potentials as the parametric variables to couple the voltage and current equations. In the present drift-diffusion theory, the very many current terms are identified by their mobility multiplier for the components of drift current,and the diffusivity multiplier for the components of the diffusion current. Complete analytical driftdiffusion equations are presented to give the DC current-voltage characteristics of four common MOS transistor structures. The drift current consists of four terms: 1-D (One-Dimensional) bulk charge drift term, 1-D carrier space-charge drift term,l-D Ex^2 (transverse electric field) drift term,2-D drift term. The diffusion current consists of three terms: 1-D bulk charge diffusion term,l-D carrier space-charge diffusion term,and 2-D diffusion term. The 1-D Ex^2 drift term was missed by all the existing transistor theories, and contributes significantly, as much as 25 % of the total current when the base layer is nearly pure. The 2-D terms come from longitudinal gradient of the longitudinal electric field,which scales as the square of the Debye to Channel length ratio, at 25nm channel length with nearly pure base, (LD/L)^2 = 10^6 but with impurity concentration of 10^18cm^-3 , (LD/L)^2 = 10^-2 .展开更多
The bipolar theory of field-effect transistor is introduced to replace the 55-year-old classic unipolar theory invented by Shockley in 1952 in order to account for the characteristics observed in recent double-gate na...The bipolar theory of field-effect transistor is introduced to replace the 55-year-old classic unipolar theory invented by Shockley in 1952 in order to account for the characteristics observed in recent double-gate nanometer silicon MOS field-effect transistors. Two electron and two hole surface channels are simultaneously present in all channel current ranges. Output and transfer characteristics are computed over practical base and gate oxide thicknesses. The bipolar theory corroborates well with experimental data reported recently for FinFETs with metal/silicon and p/n junction source/drain contacts. Single-device realization of CMOS inverter and SRAM memory circuit functions are recognized.展开更多
This paper describes the short channel theory of the bipolar field-effect transistor (BiFET) by partitioning the transistor into two sections,the source and drain sections,each can operate as the electron or hole em...This paper describes the short channel theory of the bipolar field-effect transistor (BiFET) by partitioning the transistor into two sections,the source and drain sections,each can operate as the electron or hole emitter or collector under specific combinations of applied terminal voltages. Analytical solution is obtained in the source and drain sections by separating the two-dimensional trap-free Shockley Equations into two one-dimensional equations parametrically coupled via the surface-electric-potential and by using electron current continuity and hole current continuity at the boundary between the emitter and collector sections. Total and electron-hole-channel components of the output and transfer currents and conductances, and the electrical lengths of the two sections are computed and presented in graphs as a function of the D. C. terminal voltages for the model transistor with two identical and connected metal-oxide-silicon-gates (MOS-gates) on a thin pure-silicon base over practical ranges of thicknesses of the silicon base and gate oxide. Deviations of the long physical channel currents and conductances from those of the short electrical channels are reported.展开更多
This paper gives the short channel analytical theory of the bipolar field-effect transistor (BiFET) with the drift and diffusion currents separately computed in the analytical theory. As in the last-month paper whic...This paper gives the short channel analytical theory of the bipolar field-effect transistor (BiFET) with the drift and diffusion currents separately computed in the analytical theory. As in the last-month paper which represented the drift and diffusion current by the single electrochemical (potential-gradient) current, the two-dimensional transistor is partitioned into two sections, the source and drain sections, each can operate as the electron or hole emitter or collector under specific combinations of applied terminal voltages. Analytical solution is then obtained in the source and drain sections by separating the two-dimensional trap-free Shockley Equations into two one-dimensional equations parametrically coupled via the surface-electric-potential and by using electron current continuity and hole current continuity at the boundary between the emitter and collector sections. Total and the drift and diffusion components of the electron-channel and hole-channel currents and output and transfer conductances, and the electrical lengths of the two sections are computed and presented in graphs as a function of the D. C. terminal voltages for the model transistor with two identical and connected metal-oxide-silicon-gates (MOS-gates) on a thin pure-silicon base over practical ranges of thicknesses of the silicon base and gate oxide. Deviations of the two-section short-channel theory from the one-section long-channel theory are described.展开更多
The field-effect transistor is inherently bipolar, having simultaneously electron and hole surface and volume channels and currents. The channels and currents are controlled by one or more externally applied transvers...The field-effect transistor is inherently bipolar, having simultaneously electron and hole surface and volume channels and currents. The channels and currents are controlled by one or more externally applied transverse electric fields. It has been known as the unipolar field-effect transistor for 55-years since Shockley's 1952 invention,because the electron-current theory inevitably neglected the hole current from over-specified internal and boundary conditions, such as the electrical neutrality and the constant hole-electrochemical-potential, resulting in erroneous solutions of the internal and terminal electrical characteristics from the electron channel current alone, which are in gross error when the neglected hole current becomes comparable to the electron current, both in subthreshold and strong inversion. This report presents the general theory, that includes both electron and hole channels and currents. The rectangular ( x, y, z) parallelepiped transistors,uniform in the width direction (z-axis),with one or two MOS gates on thin and thick,and pure and impure base, are used to illustrate the two-dimensional effects and the correct internal and boundary conditions for the electric and the electron and hole electrochemical potentials. Complete analytical equations of the DC current-voltage characteristics of four common MOS transistor structures are derived without over-specification: the 1-gate on semi-infinite-thick impure-base (the traditional bulk transistor), the 1-gate on thin impure-silicon layer over oxide-insulated silicon bulk (SOI) ,the 1-gate on thin impure-silicon layer deposited on insulating glass (SOI TFT), and the 2-gates on thin pure-base (FinFETs).展开更多
A compact model for the integrated inversion charge density Qi in double-gate (DG-) MOSFETs is developed. For nanoscale applications,quantum confinement of the inversion carriers must be taken into account. Based on...A compact model for the integrated inversion charge density Qi in double-gate (DG-) MOSFETs is developed. For nanoscale applications,quantum confinement of the inversion carriers must be taken into account. Based on the previous work of Ge, we establish an expression for the surface potential with respect to Qi, and form an implicit equation, from which Qi can be solved. Results predicted by our model are compared to published data as well as results from Schred,a popular 1D numerical solver that solves the Poisson's and Schr6dinger equa- tions self-consistently. Good agreement is obtained for a wide range of silicon layer thickness,confirming the supe- riority of this model over previous work in this field.展开更多
Based on the exact resultant solution of two-dimensional Poisson's equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have bee...Based on the exact resultant solution of two-dimensional Poisson's equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor (CMOS)-based device in a nanoscale regime.展开更多
A surface potential-based model for undoped symmetric double-gate MOSFETs is derived by solving Poisson's equation to obtain the relationship between the surface potential and voltage in the channel region in a self-...A surface potential-based model for undoped symmetric double-gate MOSFETs is derived by solving Poisson's equation to obtain the relationship between the surface potential and voltage in the channel region in a self-consistent way. The drain current expression is then obtained from Pao-Sah's double integral. The model consists of one set of surface potential equations,and the analytic drain current can be evaluated from the surface potential at the source and drain ends. It is demonstrated that the model is valid for all operation regions of the double-gate MOSFETs and without any need for simplification (e. g., by using the charge sheet assumption) or auxiliary fitting functions. The model has been verified by extensive comparisons with 2D numerical simulation under different operation conditions with different geometries. The consistency between the model calculation and numerical simulation demonstrates the accuracy of the model.展开更多
A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs.Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI...A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs.Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI MOSFETs is also carried out.Finally this work is concluded by modeling the cut-off frequency, which is one of the main figures of merit for analog/RF performance for double-gate fully depleted nanoscale SOI MOSFETs.The results of the modeling are compared with those obtained by a 2D ATLAS device simulator to verify the accuracy of the proposed model.展开更多
文摘A novel planar DGDT FDSOI nMOSFET is presented, and the operation mechanism is discussed. The device fabrication processes and characteristics are simulated with Tsuprem 4 and Medici. The back-gate n-well is formed by implantation of phosphorus at a dosage of 3 × 10^13 cm^-2 and an energy of 250keV and connected directly to a front-gate n^+ polysilicon. This method is completely compatible with the conventional bulk silicon process. Simulation results show that a DGDT FDSOI nMOSFET not only retains the advantages of a conventional FDSOI nMOSFET over a partially depleted (PD) SOI nMOSFET--that is the avoidance of anomalous subthreshold slope and kink effects but also shows a better drivability than a conventional FDSOI nMOSFET.
文摘A quasi two-dimensional (2D) analytical model of a double-gate (DG) MOSFET with Schottky source/drain is developed based on the Poisson equation.The 2D potential distribution in the channel is calculated.An expression for threshold voltage for a short-channel DG MOSFET with Schottky S/D is also presented by defining the turn-on condition.The results of the model are verified by the numerical simulator DESSIS-ISE.
基金Project supported by the National Natural Science Foundation of China(Grant No.60876027)the Open Funds of Jiangsu Province Key Lab of ASIC Design(JSICK1007)
文摘A continuous yet analytic channel potential solution is proposed for doped symmetric double-gate (DG) MOSFETs from the accumulation to the strong-inversion region. Analytical channel potential relationship is derived from the complete 1-D Poisson equation physically, and the channel potential solution of the DG MOSFET is obtained analytically. The extensive comparisons between the presented solution and the numerical simulation illustrate that the solution is not only accurate and continuous in the whole operation regime of DG MOSFETs, but also valid to wide doping concentration and various geometrical sizes, without employing any fitting parameter.
文摘The electrical characteristics of a double-gate armchair silicene nanoribbon field-effect-transistor (DG ASiNR FET) are thoroughly investigated by using a ballistic quantum transport model based on non-equilibrium Green's function (NEGF) approach self-consistently coupled with a three-dimensional (3D) Poisson equation. We evaluate the influence of variation in uniaxial tensile strain, ribbon temperature and oxide thickness on the on-off current ratio, subthreshold swing, transconductance and the delay time of a 12-nm-length ultranarrow ASiNR FET. A novel two-parameter strain mag- nitude and temperature-dependent model is presented for designing an optimized device possessing balanced amelioration of all the electrical parameters. We demonstrate that employing HfO2 as the gate insulator can be a favorable choice and simultaneous use of it with proper combination of temperature and strain magnitude can achieve better device performance. Furthermore, a general model power (GMP) is derived which explicitly provides the electron effective mass as a function of the bandgap of a hydrogen passivated ASiNR under strain.
基金Project supported by the National Natural Science Foundation of China (Grant No.60876027)the National Science Foundation for Distinguished Young Scholars of China (Grant No.60925015)+1 种基金the National Basic Research Program of China (Grant No.2011CBA00600)the Fundamental Research Project of Shenzhen Science & Technology Foundation,China (Grant No.JC200903160353A)
文摘As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET. Time efficiency is one of the most important requirements for device modeling. In this paper, an improvement to the computational efficiency of the drain current model for double-gate MOSFETs is extended, and different calculation methods are compared and discussed. The results show that the calculation speed of the improved model is substantially enhanced. A two-dimensional device simulation is performed to verify the improved model. Furthermore, the model is implemented into the HSPICE circuit simulator in Verilog-A for practical application.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.60976068and60936005)the Cultivation Fund of the Major Science and Technology Innovation,Ministry of Education,China(Grant No.708083)+1 种基金Specialized Research Fund for the Doctoral Program of Higher Education(Grant No.200807010010)the Fundamental Research Funds for the Central Universities
文摘This paper develops the simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET. The models mainly include the analytical equations of the surface potential, surface electric field and threshold voltage, which are derived by solving two dimensional Poisson equation in strained-Si layer. The models are verified by numerical simulation. Besides offering the physical insight into device physics in the model, the new structure also provides the basic designing guidance for further immunity of short channel effect and draininduced barrier-lowering of CMOS-based devices in nanometre scale.
基金supported by Women Scientist Scheme-A, Department of Science and Technology, New Delhi, Government of India, under the Grant SR/WOS-A/ET-5/2017
文摘This paper presents a compact two-dimensional analytical device model of surface potential,in addition to electric field of triple-material double-gate(TMDG)tunnel FET.The TMDG TFET device model is developed using a parabolic approximation method in the channel depletion space and a boundary state of affairs across the drain and source.The TMDG TFET device is used to analyze the electrical performance of the TMDG structure in terms of changes in potential voltage,lateral and vertical electric field.Because the TMDG TFET has a simple compact structure,the surface potential is computationally efficient and,therefore,may be utilized to analyze and characterize the gate-controlled devices.Furthermore,using Kane's model,the current across the drain can be modeled.The graph results achieved from this device model are close to the data collected from the technology computer aided design(TCAD)simulation.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61376099,11235008,and 61205003)
文摘The two-dimensional models for symmetrical double-material double-gate (DM-DG) strained Si (s-Si) metal-oxide semiconductor field effect transistors (MOSFETs) are presented. The surface potential and the surface electric field ex- pressions have been obtained by solving Poisson's equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate (SM-DG) MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.
基金Project supported by the National Natural Science Foundation of China (Grant No 60625403)the Special Funds for MajorState Basic Research (973) Projects and NCET program
文摘A novel double-gate (DG) junction field effect transistor (JFET) with depletion operation mode is proposed in this paper. Compared with the conventional DG MOSFET, the novel DG JFET can achieve excellent performance with square body design, which relaxes the requirement on silicon film thickness of DG devices. Moreover, due to the structural symmetry, both p-type and n-type devices can be realized on exactly the same structure, which greatly simplifies integration. It can reduce the delay by about 60% in comparison with the conventional DG MOSFETs.
文摘In this paper, we have investigated the design parameters of RF CMOS switch, which will be used for the wireless tele-communication systems. A double-pole four-throw double-gate radio-frequency complementary-metal-oxide-semicon- ductor (DP4T DG RF CMOS) switch for operating at the 1 GHz is implemented with 45-nm CMOS process technology. This proposed RF switch is capable to select the data streams from the two antennas for both the transmitting and receiving processes. For the development of this DP4T DG RF CMOS switch we have explored the basic concept of the proposed switch circuit elements required for the radio frequency systems such as drain current, threshold voltage, resonant frequency, return loss, transmission loss, VSWR, resistances, capacitances, and switching speed.
文摘In this paper, we have analyzed the Double-Pole Four-Throw Double-Gate Radio-Frequency Complementary Metal-Oxide-Semiconductor (DP4T DG RF CMOS) switch using S-parameters for 1 GHz to 60 GHz of frequency range. DP4T DG RF CMOS switch for operation at high frequency is also analyzed with its capacitive model. The re-sults for the development of this proposed switch include the basics of the circuit elements in terms of capacitance, re-sistance, impedance, admittance, series equivalent and parallel equivalent of this network at different frequencies which are present in this switch whatever they are ON or OFF.
文摘The previous report (XI) gave the electrochemical-potential theory of the Bipolar Field-Effect Transistors. This report (XII) gives the drift-diffusion theory. Both treat 1-gate and 2-gate, pure-base and impure-base, and thin and thick base. Both utilize the surface and bulk potentials as the parametric variables to couple the voltage and current equations. In the present drift-diffusion theory, the very many current terms are identified by their mobility multiplier for the components of drift current,and the diffusivity multiplier for the components of the diffusion current. Complete analytical driftdiffusion equations are presented to give the DC current-voltage characteristics of four common MOS transistor structures. The drift current consists of four terms: 1-D (One-Dimensional) bulk charge drift term, 1-D carrier space-charge drift term,l-D Ex^2 (transverse electric field) drift term,2-D drift term. The diffusion current consists of three terms: 1-D bulk charge diffusion term,l-D carrier space-charge diffusion term,and 2-D diffusion term. The 1-D Ex^2 drift term was missed by all the existing transistor theories, and contributes significantly, as much as 25 % of the total current when the base layer is nearly pure. The 2-D terms come from longitudinal gradient of the longitudinal electric field,which scales as the square of the Debye to Channel length ratio, at 25nm channel length with nearly pure base, (LD/L)^2 = 10^6 but with impurity concentration of 10^18cm^-3 , (LD/L)^2 = 10^-2 .
文摘The bipolar theory of field-effect transistor is introduced to replace the 55-year-old classic unipolar theory invented by Shockley in 1952 in order to account for the characteristics observed in recent double-gate nanometer silicon MOS field-effect transistors. Two electron and two hole surface channels are simultaneously present in all channel current ranges. Output and transfer characteristics are computed over practical base and gate oxide thicknesses. The bipolar theory corroborates well with experimental data reported recently for FinFETs with metal/silicon and p/n junction source/drain contacts. Single-device realization of CMOS inverter and SRAM memory circuit functions are recognized.
文摘This paper describes the short channel theory of the bipolar field-effect transistor (BiFET) by partitioning the transistor into two sections,the source and drain sections,each can operate as the electron or hole emitter or collector under specific combinations of applied terminal voltages. Analytical solution is obtained in the source and drain sections by separating the two-dimensional trap-free Shockley Equations into two one-dimensional equations parametrically coupled via the surface-electric-potential and by using electron current continuity and hole current continuity at the boundary between the emitter and collector sections. Total and electron-hole-channel components of the output and transfer currents and conductances, and the electrical lengths of the two sections are computed and presented in graphs as a function of the D. C. terminal voltages for the model transistor with two identical and connected metal-oxide-silicon-gates (MOS-gates) on a thin pure-silicon base over practical ranges of thicknesses of the silicon base and gate oxide. Deviations of the long physical channel currents and conductances from those of the short electrical channels are reported.
文摘This paper gives the short channel analytical theory of the bipolar field-effect transistor (BiFET) with the drift and diffusion currents separately computed in the analytical theory. As in the last-month paper which represented the drift and diffusion current by the single electrochemical (potential-gradient) current, the two-dimensional transistor is partitioned into two sections, the source and drain sections, each can operate as the electron or hole emitter or collector under specific combinations of applied terminal voltages. Analytical solution is then obtained in the source and drain sections by separating the two-dimensional trap-free Shockley Equations into two one-dimensional equations parametrically coupled via the surface-electric-potential and by using electron current continuity and hole current continuity at the boundary between the emitter and collector sections. Total and the drift and diffusion components of the electron-channel and hole-channel currents and output and transfer conductances, and the electrical lengths of the two sections are computed and presented in graphs as a function of the D. C. terminal voltages for the model transistor with two identical and connected metal-oxide-silicon-gates (MOS-gates) on a thin pure-silicon base over practical ranges of thicknesses of the silicon base and gate oxide. Deviations of the two-section short-channel theory from the one-section long-channel theory are described.
文摘The field-effect transistor is inherently bipolar, having simultaneously electron and hole surface and volume channels and currents. The channels and currents are controlled by one or more externally applied transverse electric fields. It has been known as the unipolar field-effect transistor for 55-years since Shockley's 1952 invention,because the electron-current theory inevitably neglected the hole current from over-specified internal and boundary conditions, such as the electrical neutrality and the constant hole-electrochemical-potential, resulting in erroneous solutions of the internal and terminal electrical characteristics from the electron channel current alone, which are in gross error when the neglected hole current becomes comparable to the electron current, both in subthreshold and strong inversion. This report presents the general theory, that includes both electron and hole channels and currents. The rectangular ( x, y, z) parallelepiped transistors,uniform in the width direction (z-axis),with one or two MOS gates on thin and thick,and pure and impure base, are used to illustrate the two-dimensional effects and the correct internal and boundary conditions for the electric and the electron and hole electrochemical potentials. Complete analytical equations of the DC current-voltage characteristics of four common MOS transistor structures are derived without over-specification: the 1-gate on semi-infinite-thick impure-base (the traditional bulk transistor), the 1-gate on thin impure-silicon layer over oxide-insulated silicon bulk (SOI) ,the 1-gate on thin impure-silicon layer deposited on insulating glass (SOI TFT), and the 2-gates on thin pure-base (FinFETs).
文摘A compact model for the integrated inversion charge density Qi in double-gate (DG-) MOSFETs is developed. For nanoscale applications,quantum confinement of the inversion carriers must be taken into account. Based on the previous work of Ge, we establish an expression for the surface potential with respect to Qi, and form an implicit equation, from which Qi can be solved. Results predicted by our model are compared to published data as well as results from Schred,a popular 1D numerical solver that solves the Poisson's and Schr6dinger equa- tions self-consistently. Good agreement is obtained for a wide range of silicon layer thickness,confirming the supe- riority of this model over previous work in this field.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60976068 and 60936005)Cultivation Fund of the Key Scientific and Technical Innovation Project, Ministry of Education of China (Grant No. 708083),Cultivation Fund of the Key Scientific and Technical Innovation Project, Ministry of Education of China (Grant No. 200807010010)
文摘Based on the exact resultant solution of two-dimensional Poisson's equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor (CMOS)-based device in a nanoscale regime.
基金the National Natural Science Foundation of China(No.90607017)the Competitive Ear marked Grant 611207 from the Research Grant Council of Hong Kong SARthe International Joint Research Program(NEDO Grant)from Japan(No.NEDOO5/06.EG01)~~
文摘A surface potential-based model for undoped symmetric double-gate MOSFETs is derived by solving Poisson's equation to obtain the relationship between the surface potential and voltage in the channel region in a self-consistent way. The drain current expression is then obtained from Pao-Sah's double integral. The model consists of one set of surface potential equations,and the analytic drain current can be evaluated from the surface potential at the source and drain ends. It is demonstrated that the model is valid for all operation regions of the double-gate MOSFETs and without any need for simplification (e. g., by using the charge sheet assumption) or auxiliary fitting functions. The model has been verified by extensive comparisons with 2D numerical simulation under different operation conditions with different geometries. The consistency between the model calculation and numerical simulation demonstrates the accuracy of the model.
文摘A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs.Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI MOSFETs is also carried out.Finally this work is concluded by modeling the cut-off frequency, which is one of the main figures of merit for analog/RF performance for double-gate fully depleted nanoscale SOI MOSFETs.The results of the modeling are compared with those obtained by a 2D ATLAS device simulator to verify the accuracy of the proposed model.